Buried Oxide Isolation in Multi-Gate FETs for Leakage Control
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Solution Overview
Problem
Multi-gate transistors, such as gate-all-around FETs, face issues with current leakage due to heavily doped epitaxial source/drain features and variations in epitaxial feature depths, which affect device performance and require improved isolation structures.
Innovation Solution
A dielectric oxide layer is embedded or buried in the semiconductor substrate to isolate epitaxial source/drain features, minimizing current leakage by forming a semiconductor substrate with an oxide layer and a multi-layer structure, and using oxygen implantation and annealing processes to create a buried oxide layer that retards leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If heavily doped epitaxial source/drain features are used in multi-gate transistors, then device drive current is improved, but current leakage between source/drain features and substrate increases
Solution Approach 1:
The substrate is segmented into isolated regions by embedding dielectric oxide layers between adjacent epitaxial source/drain features. This segmentation creates electrical isolation that prevents current leakage while allowing each region to maintain its heavily doped epitaxial features for high drive current operation.
Solution Approach 2:
A dielectric oxide layer is introduced as an intermediary material between the heavily doped epitaxial source/drain features and the substrate. This intermediary layer acts as an electrical insulator that blocks current leakage paths while allowing the epitaxial features to function properly.
2Ease of manufacture
If epitaxial source/drain features are formed without buried oxide isolation, then manufacturing process is simpler, but current leakage and device performance variation increase
Solution Approach 1:
The dielectric oxide layer is formed in the substrate before epitaxial source/drain features are grown. This preliminary action of embedding the oxide layer during substrate preparation ensures that isolation is established before doping and epitaxial growth, preventing current leakage from occurring in the first place while maintaining a relatively straightforward manufacturing flow.
3Reliability
If isolation structures are added to reduce current leakage, then device reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The formation of the dielectric oxide layer is merged with the substrate preparation process. By embedding the oxide layer during initial substrate formation rather than adding it as a separate subsequent step, the isolation structure is integrated into the existing manufacturing flow, minimizing additional process complexity while achieving reliable current leakage reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buried oxide layer effectively reduces or eliminates current leakage between epitaxial source/drain features and the substrate, enhancing the performance of gate-all-around FETs by improving gate control and uniformity of device features.
Implementation Method 1
an oxide layer embedded or buried in the semiconductor substrate and configured to isolate the epitaxial source/drain features from one another and from the substrate
Implementation Method 2
using oxygen implantation and annealing processes to create a buried oxide layer
Implementation Method 3
using oxygen implantation and annealing processes to create a buried oxide layer
Data Source
AI summary
A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.