Buried Oxide Interconnects for Transistor Body Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits with logic circuits face increased area and cost due to metal interconnects and contacts used to apply bias to metal oxide semiconductor (MOS) transistors, which can be mitigated by using through-substrate vias (TSVs) and buried interconnects to provide electrical connections.
Innovation Solution
The integration of a buried oxide layer with lateral buried interconnects and through-substrate vias (TSVs) allows for electrical coupling of MOS transistor bodies, reducing the need for metal interconnects and contacts, thereby minimizing the integrated circuit area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal interconnects and contacts are used to apply bias to MOS transistor bodies, then electrical connection is achieved, but the area of the logic circuits increases
Solution Approach 1:
The patent transitions from planar metal interconnects to three-dimensional buried interconnects formed within the substrate. By creating conductive paths that extend vertically through the substrate and laterally within isolation regions, the design utilizes the third dimension to reduce surface area consumption while maintaining electrical connectivity to transistor bodies.
Solution Approach 2:
The patent introduces buried interconnect structures as intermediary elements between external bias sources and transistor bodies. These buried interconnects, formed in isolation regions beneath the active device layer, serve as intermediate conductive pathways that eliminate the need for extensive top-layer metal interconnects and contacts.
2Reliability
If metal interconnects and contacts are used to apply bias to MOS transistor bodies, then electrical connection is achieved, but the cost of the integrated circuit increases
Solution Approach 1:
The patent merges the formation of buried interconnects with the existing isolation region structure. By integrating conductive paths within the isolation regions during the same fabrication sequence, the design eliminates separate manufacturing steps for additional metal interconnects and contacts, thereby reducing process complexity and manufacturing cost.
Solution Approach 2:
The buried interconnect structures serve multiple functions: they provide electrical bias to transistor bodies, act as isolation structures, and serve as integration pathways for through-substrate vias. This multi-functionality reduces the need for separate dedicated interconnect structures, simplifying the overall device architecture and reducing manufacturing cost.
3Area of stationary object
If through-substrate vias and buried interconnects are used to provide electrical connections, then the area of the integrated circuit is reduced, but the device complexity increases
Solution Approach 1:
The patent segments the electrical connection path into distinct components: through-substrate vias that penetrate the substrate, buried interconnects within isolation regions, and contact points at the device layer. This segmentation allows each component to be optimized independently and integrated systematically, managing complexity through modular design.
Solution Approach 2:
The patent performs preliminary formation of buried interconnects within isolation regions before final device assembly. By pre-establishing these conductive pathways in the substrate, the design simplifies subsequent integration steps and reduces the complexity of coordinating multiple simultaneous processes.
Data Source
AI summary
An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried interconnect extends laterally past the TSV. The integrated circuit is formed by starting with a substrate, forming the buried oxide layer with the buried interconnect at a top surface of the substrate, and forming a semiconductor device layer over the buried oxide layer. The MOS transistor is formed in the semiconductor device layer so that the body makes an electrical connection to the buried interconnect. Subsequently, the TSV is formed through a bottom surface of the substrate so as to make an electrical connection to the buried interconnect in the buried oxide layer. A body of a transistor is electrically coupled to the TSV through the buried interconnect.