Buried Oxide Isolation for Multi-Gate FET Leakage

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Solution Overview

Problem

Multi-gate transistors, such as gate-all-around FETs, face issues with current leakage due to heavily doped epitaxial source/drain features and variations in their depths, which affect the performance and reliability of semiconductor devices.

Innovation Solution

A dielectric oxide layer is embedded or buried in the semiconductor substrate to isolate epitaxial source/drain features, minimizing current leakage by forming a barrier between these features and the substrate, and optimizing the depth and thickness of this oxide layer to prevent leakage while maintaining crystal structure integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If heavily doped epitaxial source/drain features are formed in multi-gate transistors, then device drive current is improved, but current leakage between source/drain features and substrate increases

Engineering Contradiction:
Improvedevice drive currentVSAvoidcurrent leakage
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

An oxide layer is introduced as an intermediary barrier between the heavily doped epitaxial source/drain features and the substrate. This oxide layer acts as a mediator that prevents direct electrical contact and current leakage paths while allowing the heavily doped source/drain features to maintain their high drive current capability. The oxide layer is formed at specific depths and thicknesses to optimally block leakage currents without compromising the electrical performance of the device.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The substrate region is segmented into multiple zones with different electrical properties: the original substrate, the oxide layer region, and the epitaxial source/drain regions. This segmentation creates distinct electrical domains where the oxide layer forms an isolated region that breaks the continuous conductive path between the heavily doped source/drain features and the substrate, thereby preventing leakage while preserving drive current.

Inventive Principle:
Principle #1Segmentation

2Reliability

If S/D recess depth is increased to improve device performance, then gate control is enhanced, but variation in epitaxial source/drain feature depths increases causing current leakage

Engineering Contradiction:
Improvegate controlVSAvoidepitaxial source/drain feature depth uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The oxide layer is formed in the substrate before the epitaxial source/drain features are grown. This preliminary formation of the oxide barrier ensures that even if there are variations in the depth of the epitaxial features due to manufacturing tolerances, the oxide layer is already in place to prevent current leakage. The oxide layer acts as a pre-established protective barrier that compensates for depth variations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The oxide layer parameters (depth and thickness) are optimized to provide effective leakage blocking while being tolerant to variations in epitaxial feature depth. By carefully controlling the oxide layer formation depth and thickness parameters, the design achieves robust performance that maintains gate control benefits while compensating for manufacturing variations in the epitaxial growth process.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The oxide layer effectively reduces or eliminates current leakage between epitaxial source/drain features and the substrate, enhancing the performance and reliability of gate-all-around FETs by improving gate control and uniformity in device manufacturing.

Implementation Method 1

A dielectric oxide layer is embedded or buried in the semiconductor substrate to isolate epitaxial source/drain features, minimizing current leakage by forming a barrier between these features and the substrate

Methodology Applied
Scientific EffectDielectric barrier: Dielectric

Data Source

PatentUS11444179B2Isolation structures in multi-gate semiconductor devices and methods of fabricating the same
Publication Date: 2022.09.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11444179B2 patent drawing
  • US11444179B2 patent drawing
  • US11444179B2 patent drawing

AI summary

A semiconductor structure includes a semiconductor substrate, an oxide layer disposed over the semiconductor substrate, a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers, and an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.