Buried Pad Routing in GAA Isolation for Compact Layouts
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Solution Overview
Problem
As feature size of semiconductor devices decreases, there is a challenge in optimizing circuit layouts due to space constraints, particularly in integrating gate-all-around transistor structures with conventional routing methods.
Innovation Solution
The integration of buried conductive pads within isolation structures, such as shallow trench isolation, allows for enhanced routing flexibility and reduced area requirements by forming these pads in multiple dimensions, specifically in gate-all-around transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional routing methods are used with gate-all-around transistor structures, then routing simplicity is maintained, but space utilization deteriorates and area requirements increase
Solution Approach 1:
The patent implements buried conductive pads extending in multiple dimensions within the isolation structure, specifically in two-dimensional planes beneath the transistor structures. This dimensional transformation allows electrical connections to be established without occupying additional lateral space, thereby reducing area requirements while maintaining routing flexibility through three-dimensional path options.
Solution Approach 2:
The buried conductive pads are nested within the isolation structure, placing conductive elements inside the existing isolation regions rather than adding separate routing layers. This nesting approach allows routing functionality to be integrated within the isolation structure itself, reducing overall device area while preserving routing capabilities.
2Productivity
If feature size decreases, then device density improves, but space constraints worsen
Solution Approach 1:
By moving conductive pads into the vertical dimension within the isolation structure, the patent enables continued device density improvement without proportionally increasing lateral space requirements. The multi-dimensional routing approach allows compact feature sizes while maintaining adequate spacing for electrical connections.
3Area of stationary object
If central poly pitch is reduced, then circuit layout compactness improves, but manufacturing precision requirements worsen
Solution Approach 1:
The buried conductive pads are formed within the isolation structure using the same processing steps as the isolation formation itself, nesting the conductive element creation within the existing manufacturing flow. This approach reduces the need for additional high-precision alignment steps, allowing central poly pitch reduction without proportionally increasing manufacturing complexity.
Data Source
AI summary
A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.