Buried Photodiode Parallel Capacitor Linearity Dynamic Range
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Solution Overview
Problem
Buried photodiodes suffer from reduced junction capacitance due to complete depletion, limiting the dynamic range and causing charge saturation, which restricts the expansion of the dynamic range and linearity in solid-state imaging devices.
Innovation Solution
Incorporating a capacitive element in parallel with the buried photodiode to accumulate charges generated by incident light, allowing for improved linearity and dynamic range, while maintaining the buried photodiode's ability to detect light through the capacitive element, thus reducing the pixel portion layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complete depletion of the second semiconductor region is achieved to reduce junction capacitance, then linearity and S/N ratio are improved, but dynamic range is reduced due to charge saturation
Solution Approach 1:
The patent divides the charge accumulation function into two separate components: the buried photodiode maintains complete depletion for linear charge generation, while a separate capacitive element (surface capacitor) provides additional charge storage capacity. This segmentation allows the system to achieve both high linearity and expanded dynamic range by combining the advantages of complete depletion with additional charge holding capability.
2Reliability
If complete depletion of the second semiconductor region is achieved to reduce junction capacitance, then S/N ratio is improved, but dynamic range is reduced due to charge saturation
Solution Approach 1:
The patent separates the charge generation and charge storage functions into distinct components. The buried photodiode's second semiconductor region is completely depleted to minimize junction capacitance and improve S/N ratio, while the separately formed capacitive element provides additional charge storage capacity to expand dynamic range without compromising the low-capacitance advantage.
3Adaptability or versatility
If a capacitive element is added in parallel to the buried photodiode, then dynamic range and linearity are improved, but device complexity increases
Solution Approach 1:
The patent merges the capacitive element with the existing photodiode structure by forming it in the same semiconductor substrate using the same doping processes. The capacitive element is integrated into the pixel portion layout, sharing space with the buried photodiode structure, thereby reducing the overall device complexity compared to using completely separate components.
Solution Approach 2:
The added capacitive element serves multiple functions: it extends the dynamic range by providing additional charge storage capacity, maintains linearity through its parallel connection with the depleted photodiode, and can be formed using the same semiconductor processing steps as the photodiode itself, thereby reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances both the linearity and dynamic range of the solid-state imaging device by preventing charge saturation in the junction capacitor and improving the signal-to-noise ratio through complete depletion of the second semiconductor region, while ensuring the buried photodiode's sensitivity and photodetecting area are maintained without increasing the pixel portion layout area.
Implementation Method 1
a buried photodiode for generating charges of an amount corresponding to the intensity of incident light
Implementation Method 2
a capacitive element connected in parallel to the buried photodiode to accumulate charges generated in the buried photodiode
Data Source
AI summary
There is provided a solid-state imaging device with an improved linearity as well as dynamic range. Each pixel portion Pm,n in the solid-state imaging device includes: a buried photodiode PD for generating charges of an amount corresponding to the intensity of incident light; a capacitive element C connected in parallel to the buried photodiode PD to accumulate charges generated in the buried photodiode PD; an amplifying transistor T1 for outputting a voltage value corresponding to a voltage value input to the gate terminal; a transferring transistor T2 for inputting a voltage value corresponding to the amount of accumulated charges in the capacitive element C to the gate terminal of the amplifying transistor T1; a discharging transistor T3 for discharging the charges of the capacitive element C; and a selecting transistor T4 for selectively outputting a voltage value output from the amplifying transistor T1 to a wiring Ln.