Buried Pipe Gate Electrode for Nonvolatile Memory Resistance
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Solution Overview
Problem
In three-dimensional nonvolatile memory devices with U-shaped channel layers, the electric resistance of pipe connection transistors is a concern due to the limited height of their polysilicon gate electrodes, which can restrict further reduction in resistance.
Innovation Solution
The lower part of the pipe connection gate electrode is buried in a substrate groove, increasing its volume without significantly increasing height, and the device includes pipe channel layers and alternately stacked interlayer insulating and cell gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the height of the pipe connection gate electrode is increased to reduce electric resistance, then the electric resistance decreases, but the device height increases substantially which limits further improvement
Solution Approach 1:
The pipe connection gate electrode is extended in the horizontal direction by burying it in a groove within the substrate plane, rather than increasing height vertically. This dimensional shift allows the electrode to achieve greater volume and lower resistance without substantially increasing the overall device height.
Solution Approach 2:
The pipe connection gate electrode is nested within a groove formed in the substrate, allowing the electrode to be embedded in the substrate structure. This nesting approach increases the effective volume of the electrode while maintaining a compact overall device profile.
2Reliability
If the volume of the pipe connection gate electrode is increased to reduce electric resistance, then the electric resistance decreases, but the device complexity increases
Solution Approach 1:
The formation of the pipe connection gate electrode groove is merged with the existing substrate processing steps. The groove is formed using the same sacrificial layer and etching processes that are already part of the memory device fabrication sequence, thereby increasing electrode volume without adding substantial process complexity.
Solution Approach 2:
The groove for the pipe connection gate electrode is formed in advance during the substrate preparation phase, before the main memory structure fabrication begins. This preliminary action integrates the resistance-reduction feature into the existing fabrication flow without requiring separate complex processing steps.
Data Source
AI summary
This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.