Buried Poly Resistor Parasitic Capacitance Reduction
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Solution Overview
Problem
In modern integrated circuits, the shrinking size of transistors leads to challenges in forming resistors that are compatible with sophisticated gate electrode structures, as conventional buried resistor structures contribute to parasitic capacitance and complexity, while polysilicon resistors require additional deposition processes that are not compatible with high-k metal gate electrode structures.
Innovation Solution
A buried resistive structure is formed in a specified semiconductor region, enclosed by dielectric material, amorphized, and annealed to create a polycrystalline semiconductor material, reducing parasitic capacitance and allowing for enhanced flexibility in forming resistive structures compatible with conventional polycrystalline resistors, without the need for dedicated polysilicon deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional buried resistor structures are used, then resistor functionality is provided, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
The patent changes the physical state of the semiconductor material from crystalline to amorphous in the resistor region. This parameter change reduces the carrier concentration and mobility, thereby reducing parasitic capacitance while maintaining the resistor's functionality. The amorphous material provides better isolation from adjacent semiconductor areas, reducing capacitive coupling.
Solution Approach 2:
The patent applies local quality by creating a distinct amorphous region within the semiconductor layer specifically for the resistor, while leaving other regions crystalline. This localized change in material structure allows the resistor to have different electrical properties (lower parasitic capacitance) without affecting the overall device performance in other areas.
2Object-affected harmful factors
If polysilicon resistors are formed above the semiconductor layer, then parasitic capacitance is reduced, but additional deposition processes are required that are not compatible with high-k metal gate electrode structures
Solution Approach 1:
The patent merges the resistor formation process with the existing semiconductor layer processing. Instead of adding a separate polysilicon deposition step, the resistor is formed by modifying the existing semiconductor layer through ion implantation and annealing to create an amorphous region. This combines multiple functions into a single integrated process flow that is compatible with high-k metal gate structures.
Solution Approach 2:
The semiconductor layer itself serves dual purposes: it provides the active device regions (crystalline) and the resistor region (amorphous). The existing semiconductor material is transformed in-situ to create the resistor, eliminating the need for separate resistor material deposition and reducing manufacturing complexity.
3Area of stationary object
If transistor size is reduced to improve packing density, then more circuit elements fit on chip, but resistor accuracy becomes more difficult to maintain within tight tolerance ranges
Solution Approach 1:
The patent uses ion implantation to precisely control the dopant concentration in the amorphous resistor region. This parameter control allows for accurate resistance values even in small geometries. The amorphous structure provides uniform dopant distribution, ensuring consistent resistance values and tight tolerance ranges despite reduced transistor sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and enhances flexibility in forming sophisticated transistor structures, maintaining compatibility with conventional polycrystalline silicon resistors and allowing for precise resistance adjustments, thereby improving packing density and device performance.
Implementation Method 1
annealing the amorphized semiconductor material to form a polycrystalline semiconductor region
Implementation Method 2
introducing a dopant species in the amorphized semiconductor material to adjust a specific resistance of the resistive structure
Data Source
AI summary
An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.