Buried Polysilicon Resistor Under STI for Heat and Area Control
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Solution Overview
Problem
Existing IC resistors formed over STI in MOL and BEOL layers face issues with resistance variation due to temperature under high current, occupy valuable area, and require complex electrical connections, limiting thermal dissipation and access to other components.
Innovation Solution
A structure is developed with a doped buried polysilicon layer under STI and a high resistivity polysilicon layer, coupled with spaced contacts, which improves thermal dissipation and reduces area usage by allowing stacked resistors, while minimizing parasitic leakage and enhancing frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If resistors are formed over STI in MOL and BEOL layers, then thermal dissipation from the resistor into the substrate is reduced, but resistance variation due to temperature under high current occurs and valuable area is occupied
Solution Approach 1:
The patent moves the resistor from the traditional horizontal plane in MOL/BEOL layers to a vertical stacked configuration. The first resistor remains in the ILD layer over STI, while the second resistor is formed in a lower layer (such as the substrate or a lower interlayer dielectric), creating a three-dimensional stacked arrangement that reduces area occupation while maintaining thermal isolation benefits
Solution Approach 2:
The patent implements a nested structure where one resistor is positioned within the vertical projection area of another resistor. The lower resistor (second resistor) is placed beneath the upper resistor (first resistor), allowing both resistors to occupy overlapping horizontal space at different vertical levels, thereby reducing the total area required for resistor implementation
2Reliability
If resistors extend horizontally within the layers, then resistance function is achieved, but valuable area is taken up and access to other functional components is blocked
Solution Approach 1:
The patent transitions from two-dimensional horizontal resistor extension to three-dimensional vertical stacking. By forming resistors at different vertical levels (first resistor in upper ILD layer, second resistor in lower substrate or lower ILD layer), the design achieves the required resistance function while minimizing horizontal area occupation
Solution Approach 2:
The patent divides the resistor function into separate stacked components (first resistor and second resistor) positioned at different vertical levels. This segmentation allows each resistor to be independently formed and connected through contact structures, enabling area-efficient layout while maintaining individual resistance functions
3Loss of energy
If resistors are formed over STI, then thermal dissipation is reduced, but complex electrical connections are required to access components below
Solution Approach 1:
The patent makes the lower resistor (second resistor) serve dual purposes: it functions as an active resistive element and simultaneously provides a platform for forming contact structures that access the substrate or lower layers. The contact structures can penetrate through or beside the lower resistor to reach underlying components, reducing the need for separate access paths and simplifying the overall connection architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances thermal conductivity and frequency response, reduces substrate coupling, and allows for improved resistor density with reduced area, addressing resistance variation and complex connections.
Implementation Method 1
improves thermal dissipation from the resistor into the substrate
Implementation Method 2
high resistivity (HR) polysilicon layer under the doped buried polysilicon layer
Data Source
AI summary
Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.