Buried Power Interconnect Layout for Low-Leakage MOSFET Contacts
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Solution Overview
Problem
Current semiconductor devices face challenges in maintaining electrical characteristics and reliability due to leakage currents and misalignment issues in the formation of lower power interconnection lines, which affect the performance and integration of MOSFETs as device sizes are scaled down.
Innovation Solution
The implementation of a semiconductor device design that includes a substrate with specific power delivery network layers, interconnection lines, and spacers, where the lower power interconnection lines are buried in the substrate and feature a connection portion with a silicon-based insulating material, effectively reducing leakage currents and improving contact resistance by using a double-layered spacer structure with different insulating materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the lower power interconnection line is formed using conventional single-layer spacer structure, then the manufacturing process is simpler, but misalignment occurs between the lower power interconnection line and the upper contact, causing process defects
Solution Approach 1:
The spacer structure is divided into two distinct layers: a first spacer layer and a second spacer layer. The first spacer layer defines the position of the upper contact, while the second spacer layer defines the position of the lower power interconnection line. This segmentation allows each layer to be independently optimized for its specific function, thereby achieving precise alignment without complicating the overall manufacturing process.
Solution Approach 2:
The first spacer layer is formed beforehand to establish the position of the upper contact. Subsequently, the second spacer layer is formed based on the predefined position of the first spacer layer, which in turn establishes the position of the lower power interconnection line. This preliminary action ensures that alignment is built into the structure during fabrication, eliminating misalignment issues.
2Productivity
If the device size is scaled down to improve integration, then the productivity increases, but leakage currents increase and electrical characteristics deteriorate
Solution Approach 1:
The double-layer spacer structure acts as an intermediary mechanism that enables precise positioning of the lower power interconnection line relative to the upper contact. This precise positioning ensures optimal contact resistance and minimizes leakage currents, thereby maintaining reliable electrical characteristics even as device dimensions are scaled down for higher integration.
Solution Approach 2:
Different spacer layers are assigned different local functions: the first spacer layer is optimized for defining the upper contact position, while the second spacer layer is optimized for defining the lower power interconnection line position. This local quality differentiation ensures that each region of the structure contributes optimally to reducing leakage and maintaining electrical performance at scaled dimensions.
3Reliability
If the line width of interconnection lines is increased to reduce resistance, then the electrical conductivity improves, but the area occupied increases, reducing integration density
Solution Approach 1:
Instead of increasing the line width (lateral dimension) to reduce resistance, the invention utilizes the vertical dimension by implementing a double-layer spacer structure. This allows for precise positioning and optimized contact geometry in the vertical direction, thereby reducing contact resistance without increasing the lateral area occupied by the interconnection lines, maintaining high integration density.
Data Source
AI summary
A semiconductor device comprising a substrate including an active pattern, a channel pattern and a source/drain pattern that are on the active pattern, the source/drain pattern connected to the channel pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, an upper contact being adjacent to the active contact and extending into the substrate, a lower power interconnection line buried in the substrate, and a power delivery network layer on a bottom surface of the substrate, wherein the lower power interconnection line includes a connection portion connected to the upper contact, and a lower portion of the upper contact protrudes into the connection portion.