Buried Power Rail Layout for Backside Power Alignment and Resistance
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Solution Overview
Problem
The manufacturing of backside power distribution network (BSPDN) semiconductor architectures faces challenges such as misalignment between buried power rails and through-silicon vias, leading to increased resistance and device failure, as well as thermal degradation of metal materials during front-end-of-line processing.
Innovation Solution
A method of manufacturing a BSPDN semiconductor architecture involving a carrier substrate with patterned fins, oxide layers, and metal-filled trenches to form a buried power rail that extends from one surface to the other, eliminating the need for a separate through-silicon via and reducing thermal degradation by forming the BPR after FEOL layers are created.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate through-silicon via is used to connect the buried power rail, then the power distribution network can be formed, but misalignment between the via and power rail occurs leading to increased resistance
Solution Approach 1:
The patent merges the through-silicon via and buried power rail into a single integrated structure. The BPR extends continuously from the first surface to the second surface of the substrate, eliminating the need for a separate via connection. This integration removes the alignment interface between via and power rail, thereby eliminating misalignment issues and reducing resistance.
Solution Approach 2:
The patent extracts and removes the separate through-silicon via from the structure. By eliminating this intermediate component, the design directly connects the power distribution network to the buried power rail without requiring precise alignment, thus solving the misalignment problem while maintaining power distribution functionality.
2Productivity
If the buried power rail is formed before front-end-of-line processing, then the power distribution network can be established early, but thermal degradation occurs during high-temperature processing
Solution Approach 1:
The patent inverts the conventional sequence by forming the buried power rail after front-end-of-line processing rather than before. This reversal ensures that the metal BPR is not exposed to high-temperature processing conditions that would cause thermal degradation, metal migration, or diffusion, thereby maintaining device reliability while still enabling early power distribution setup in the overall manufacturing flow.
3Manufacturing precision
If the buried power rail uses metal material, then low resistance is achieved, but metal migration and diffusion occur during high-temperature processing
Solution Approach 1:
The patent performs preliminary actions by completing all high-temperature front-end-of-line processing steps before forming the metal buried power rail. This sequencing ensures that the metal material is introduced into the structure only after the substrate has already undergone thermal processing, preventing metal migration and diffusion while maintaining the low resistance benefits of metal conductors.
Data Source
AI summary
Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.