Buried Power Rail Backside Contact for Tight Device Pitch
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Solution Overview
Problem
Current methods for forming buried power rails (BPRs) face challenges such as high-aspect-ratio etching and space constraints in advanced technology nodes, hindering device pitch scaling and increasing IR drop.
Innovation Solution
A method is developed to form a buried interconnect by etching a trench underneath the source/drain region, using a dummy interconnect, and replacing it with a conductive material from the backside, allowing for backside contact and reducing space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frontside processing is used to form Via-to-BPR connections, then connections can be established between active devices and buried power rails, but high-aspect-ratio etching and space constraints occur which hinder device pitch scaling
Solution Approach 1:
The patent applies inversion by switching from frontside processing to backside processing for forming the buried interconnect connection. Instead of creating the connection from the frontside through high-aspect-ratio etching, the method forms the connection from the backside of the substrate, thereby avoiding the space constraints and high-aspect-ratio etching challenges while maintaining connection reliability
Solution Approach 2:
The patent utilizes another dimension by moving the processing approach from the frontside (vertical dimension through high-aspect-ratio etching) to the backside (horizontal dimension on the substrate surface). This dimensional shift allows the buried interconnect to be formed without occupying valuable frontside space, enabling continued device pitch scaling
2Reliability
If conventional frontside approaches are used for BPR contacting, then connections are formed, but space requirements hinder continued scaling of device pitches
Solution Approach 1:
The patent reverses the conventional approach by forming the buried interconnect connection from the backside rather than the frontside. This inversion eliminates the need for additional frontside space while maintaining reliable electrical connection between the active device and the buried power rail
Solution Approach 2:
The patent moves the connection formation process to another dimension (the backside of the substrate) where it does not compete for space with the frontside interconnect structure. This allows device pitches to continue scaling without being constrained by the space requirements of the contacting structure
3Object-affected harmful factors
If dummy interconnect and replacement method are used, then metal contamination risks are reduced and overlay control is facilitated, but additional processing steps are required
Solution Approach 1:
The patent uses a dummy interconnect as an intermediary structure that is temporarily formed during processing and then replaced with the final conductive material. This intermediary approach allows for better overlay control and reduced metal contamination risk, as the dummy structure can be formed with different materials that are less prone to contamination issues
Solution Approach 2:
The patent performs preliminary action by forming the dummy interconnect structure before the final conductive material is deposited. This preliminary structure enables precise alignment and overlay control during subsequent processing steps, while also allowing for optimization of the final metal deposition process to minimize contamination risks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient formation of buried interconnects without increasing device pitch, reduces metal contamination risks, and facilitates overlay control with transistor structures.
Implementation Method 1
forming a trench for a buried interconnect beside the first source/drain region, wherein the trench is formed by etching the substrate
Implementation Method 2
forming a dielectric liner on interior surfaces of the trench
Implementation Method 3
removing the dummy interconnect selectively to the dielectric liner
Data Source
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AI summary
The disclosure relates to a method for forming a semiconductor device, comprising: forming a transistor structure on a frontside of a substrate, the transistor structure comprising a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body comprising at least one channel layer extending horizontally between the first and second source/drain bodies; forming a trench for a buried interconnect beside the first source/drain region, wherein the trench is formed by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a dielectric liner on interior surfaces of the trench; forming an opening in the dielectric liner, underneath the first source/drain region; and subsequent to forming the opening in the dielectric liner, forming a dummy interconnect of a dummy material in the trench; wherein the method further comprises, subsequent to forming the dummy interconnect: exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the dielectric liner; and forming a buried interconnect of a conductive material in the trench, wherein the buried interconnect is connected to the first source/drain body via the opening in the dielectric liner.