Buried Power Rail Structure for Dense Chips With Lower RC Delay
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Solution Overview
Problem
The challenge in modern integrated chips is to scale down device features to increase device density without degrading performance, particularly due to increased capacitance and resistance-capacitance (RC) delay from decreased wire spacing and width, as well as design complexity and processing challenges from embedded power rails.
Innovation Solution
The solution involves embedding power rails within the semiconductor substrate directly underneath the field-effect transistors (FETs) and using source/drain contacts to electrically couple the FETs to the power rails, thereby reducing the number of conductive wires and vias in the upper interconnect structure and simplifying design and alignment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device features are scaled down to increase device density, then device density increases, but capacitance and RC delay increase degrading performance
Solution Approach 1:
The patent moves power delivery from the lateral plane (interconnect wires) to the vertical dimension (buried power rails in the substrate). This dimensional shift allows power rails to be positioned directly beneath FETs, reducing lateral wire spacing and capacitance while maintaining adequate power delivery cross-section through the vertical dimension.
Solution Approach 2:
The patent extracts the power delivery function from the upper interconnect structure and places it in the substrate. By separating power delivery (buried rails) from signal routing (upper interconnects), the patent eliminates the harmful interaction between signal wires and power rails, reducing capacitance and RC delay.
2Quantity of substance
If power rails are embedded in the substrate, then device density increases and design simplifies, but processing complexity and alignment challenges increase
Solution Approach 1:
The patent forms buried power rails in the substrate before fabricating the FETs and upper interconnect structures. This preliminary action establishes fixed reference points that simplify subsequent alignment processes, as the rails are already in place to guide FET placement and interconnect routing.
Solution Approach 2:
The buried power rails serve multiple functions automatically: they provide power delivery, act as alignment references for FETs and interconnects, and reduce capacitance by being positioned optimally beneath devices. This self-service approach reduces the need for separate alignment features and processing steps.
3Device complexity
If the number of conductive wires and vias in the upper interconnect structure is reduced, then design complexity decreases, but connectivity must be maintained
Solution Approach 1:
The patent extracts the power delivery function from the upper interconnect structure, removing power rails from the lateral wire network. This extraction reduces the number of conductive elements that must be routed and connected in the upper layers, simplifying design while maintaining connectivity through the buried substrate rails.
Solution Approach 2:
The buried power rails act as intermediaries between the substrate and the upper interconnect structure. Instead of requiring direct lateral connections between power rails and FETs in the upper layers, the vertical buried rails provide the connection path, simplifying the upper interconnect design.
Data Source
AI summary
The present disclosure relates to an integrated chip including a semiconductor structure including a gate, a first source/drain region, and a second source/drain region. A power rail is disposed under the gate, the first source/drain region, and the second source/drain region. The power rail is in electrical connection with the first source/drain region.