Buried Power Rail Structure for Memory Area Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory designs suffer from area inefficiency due to the use of frontside power rails for memory cells, leading to a need for improved area efficiency in modern memory architecture.
Innovation Solution
The implementation of a buried power rail architecture that transitions power between a backside power network and a frontside power network using transition vias, allowing the backside power network to provide power directly to both the bitcell array and control logic, thereby optimizing power distribution and reducing area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frontside power rails are used for memory cells, then power distribution to memory cells is achieved, but area efficiency deteriorates due to area penalty in fabrication
Solution Approach 1:
The patent inverts the conventional power distribution approach by moving power rails from the frontside to the backside of the substrate. Instead of routing power through the frontside where it consumes valuable area, the power rails are buried in the backside substrate, allowing power to be delivered to memory cells without occupying frontside area, thus resolving the area efficiency problem while maintaining power distribution functionality
Solution Approach 2:
The patent transitions the power rail location from a two-dimensional frontside plane to a three-dimensional backside location. By burying power rails in the backside substrate and using through-substrate vias to connect to frontside circuitry, the solution moves the power distribution infrastructure to a different spatial dimension (backside vs. frontside), eliminating the area penalty on the frontside while maintaining electrical connectivity
2Area of stationary object
If backside power network provides power directly to control logic, then area efficiency is improved, but power network complexity increases
Solution Approach 1:
The patent segments the power distribution into two distinct networks: a backside power network for providing power to both memory cells and control logic, and a frontside power network for power distribution to frontside circuitry. This segmentation allows the backside network to handle power delivery without requiring extensive frontside routing, reducing overall area usage while the modular structure helps manage the complexity of the power network architecture
Data Source
AI summary
Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.