Buried Power Rail Architecture for Memory Routing Efficiency
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Solution Overview
Problem
Conventional circuit designs face inefficiencies in metal routing of power/ground tracks within memory instances due to lack of placement priority among different power domains, leading to increased minimum lengths of power/ground tracks and routing complexities.
Innovation Solution
The implementation of buried power rail layout schemes and techniques that include routing critical signals in buried backside metal layers, utilizing graphical user interface options to enhance power/ground net routing by identifying short power tracks and inserting buried connections, and optionally utilizing user-defined power grid enhancements for porosity to optimize power distribution network architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional metal routing is used for power/ground tracks in memory instances, then routing flexibility is maintained, but routing efficiency deteriorates due to increased minimum lengths and lack of placement priority
Solution Approach 1:
The patent introduces buried power rails in the backside metal layers (below the memory instance) as a new dimensional routing path. This allows power/ground tracks to be routed underneath the memory instance rather than through the conventional top-layer metal routing, effectively adding a third dimension to the power distribution network and reducing the minimum track lengths required.
Solution Approach 2:
The power distribution network is segmented into multiple independent components: top-layer metal routing for local connections and buried backside power rails for global power/ground distribution. This segmentation allows each layer to be optimized independently, with the buried rails providing high-efficiency power delivery without interfering with the signal routing layer above.
2Adaptability or versatility
If more power domains are added to memory instances, then functionality is improved, but routing complexity increases due to lack of placement priority
Solution Approach 1:
The patent extracts the global power/ground routing function from the congested top-layer metal routing and places it in dedicated buried backside metal layers. This separation allows multiple power domains to be supported without increasing routing complexity, as the buried rails provide a clean, organized path for power distribution independent of the signal routing layer.
3Power
If wider power tracks are routed, then power delivery efficiency is improved, but routing space availability deteriorates
Solution Approach 1:
By routing wide power tracks in the buried backside metal layers underneath the memory instance, the patent provides ample cross-sectional area for high-current power delivery without consuming lateral routing space on the top layer. The buried rails can be made very wide to accommodate high power demands while the top layer remains fully available for signal routing.
Data Source
AI summary
Various implementations described herein are directed to a method for routing buried power rails underneath a memory instance. The method may identify first rails of the buried power rails disposed in a first layer and second rails of the buried power rails disposed perpendicular to the first rails in a second layer. The method may identify long rails of the first rails with a first length and short rails of the first rails with a second length that is less than the first length. The method may separately couple the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer.