Buried Power Rail Metallization for High-Aspect-Ratio Cell Scaling
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Solution Overview
Problem
The challenge in integrated circuits is the significant area occupancy by power rails due to their larger size, which is necessary for adequate resistance and power distribution, and increasing the aspect ratio of power rails introduces issues like higher contact resistance and capacitance.
Innovation Solution
The use of electroless plating to form cobalt buried power rails with a palladium seed layer, allowing for a higher aspect ratio without void formation, and positioning the power rails underneath the device to decouple their aspect ratio from signal lines, reducing resistance while maintaining low capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are made larger in size to maintain adequate resistance for power distribution, then power distribution performance is improved, but area occupancy increases significantly
Solution Approach 1:
The patent transitions power rails from a planar configuration to a three-dimensional buried structure extending into the substrate. By digging trenches into the substrate and filling them with conductive material, the power rails gain vertical dimension, allowing resistance control through depth rather than lateral width, thus reducing area occupancy while maintaining power distribution performance
Solution Approach 2:
The patent changes the geometric parameters of power rails by increasing their depth (vertical dimension) while reducing their width (lateral dimension). This parameter transformation allows the same resistance to be achieved with smaller footprint area, resolving the contradiction between power distribution performance and area occupancy
2Area of stationary object
If the aspect ratio of power rails is increased to reduce area, then area occupancy is reduced, but contact resistance and capacitance increase
Solution Approach 1:
The patent introduces an intermediary conductive layer (such as doped silicon or metallic fill) within the buried trench structure. This intermediary material provides a low-resistance path that decouples the contact resistance from the aspect ratio, allowing high aspect ratio trenches to be used without suffering from increased contact resistance or capacitance penalties
Solution Approach 2:
By moving power rails into the vertical dimension through substrate trenches, the patent achieves area reduction while the trench geometry and fill material control the electrical characteristics, preventing the expected increase in contact resistance and capacitance that would normally accompany higher aspect ratios
3Ease of operation
If power rails are positioned above the substrate surface, then ease of connection is improved, but area required in cell design increases
Solution Approach 1:
The patent inverts the conventional approach by positioning power rails below the substrate surface rather than above it. This inversion allows power distribution to occur in the vertical subsurface space, freeing up lateral cell area while connection access is provided through vertical vias that penetrate the substrate, maintaining ease of connection despite the inverted positioning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables lower resistance in power rails without increasing via resistance or capacitance, allowing for easier scaling of cell height and reducing the overall area required in cell design.
Implementation Method 1
forming, by electroless plating, a metal buried power rail in the trench in direct contact with the non-metal liner
Data Source
AI summary
A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.