Buried Power Rail Packaging With 3D Dielectric Bonding
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes, leading to inadequate performance.
Innovation Solution
A method involving the use of a device wafer with buried power rails and a support substrate bonded via a dielectric structure, coupled with passivation layers and conductive vias, to create a semiconductor device with improved electrical connectivity and reduced wear on manufacturing tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing is simpler, but reliability decreases and performance is low
Solution Approach 1:
The semiconductor device is divided into distinct functional regions: FEOL region with buried power rails, BEOL region with dielectric structures, passivation structure with conductive vias, and substrate with power network. This segmentation allows each region to be optimized independently for its specific function, improving overall reliability while managing complexity through modular design
Solution Approach 2:
The patent transitions from planar 2D packaging to 3D vertical integration by stacking multiple functional layers (FEOL, BEOL, passivation, substrate) vertically. This dimensional change enables improved electrical connectivity and heat dissipation pathways while maintaining compact package size, resolving the contradiction between reliability improvement and complexity increase
2Productivity
If conventional semiconductor packages are used, then manufacturing processes are traditional, but cost is excessive and performance is inadequate
Solution Approach 1:
Buried power rails are formed during the FEOL manufacturing stage before BEOL processing, and the substrate with power network is prepared in advance. This preliminary action enables subsequent layers to be built upon pre-established power distribution infrastructure, improving final device performance while streamlining the overall manufacturing flow
Solution Approach 2:
The substrate serves multiple functions: mechanical support, electrical power distribution through integrated power network, and heat dissipation. The dielectric structures in BEOL region provide both electrical isolation and mechanical support. This multi-functionality improves device performance by consolidating multiple requirements into fewer manufacturing steps
3Reliability
If conventional semiconductor packages are used, then package size is large, but reliability and performance are inadequate
Solution Approach 1:
The patent achieves improved reliability within a compact footprint by transitioning to 3D vertical integration. Multiple functional layers (FEOL, BEOL, passivation, substrate) are stacked vertically, enabling short electrical interconnect paths and efficient heat dissipation while maintaining small package area, thus resolving the contradiction between reliability improvement and size reduction
Data Source
AI summary
An example method of manufacturing an electronic device can include providing a device wafer including an active region comprising a front-end-of-line (FEOL) region opposite a back-end-of-line (BEOL) region. The FEOL region can include buried power rails, and the BEOL region can include a dielectric structure having a side exposed from the BEOL region. A support substrate having a substrate dielectric can be coupled to the dielectric structure. A bond interface is disposed between the substrate dielectric and the dielectric structure. A passivation structure can be provided over the FEOL region. Conductive vias can be provided through the passivation structure. The conductive vias can include a conductor coupled to the buried power rails. A substrate can be coupled to the passivation structure. The substrate can include a power network electrically coupled to the conductive vias.