Buried Power Rail Replacement for Backside Power Delivery Scaling
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Solution Overview
Problem
Existing semiconductor technologies face challenges in efficiently supplying power to transistors while minimizing the lateral size of power rails, which occupy significant area and cause resistance issues, leading to IR drop and frequency limitations.
Innovation Solution
The implementation of buried power rails beneath the physical devices, allowing for a higher aspect ratio without increasing via resistance or BEOL capacitance, and enabling self-alignment techniques for accurate placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are made larger in width to reduce resistance and maintain adequate power distribution, then power delivery performance is improved, but the area occupied by power rails within the cell design increases significantly
Solution Approach 1:
The patent transitions power rails from a planar (2D) configuration to a vertical (3D) configuration by burying them underneath transistors. This dimensional change allows the power delivery function to be achieved in the vertical dimension rather than consuming lateral cell area, resolving the contradiction between power distribution performance and cell area occupation.
Solution Approach 2:
The power rails are nested underneath the transistor structures, utilizing the vertical space below active devices. This nesting approach allows power rails to coexist with transistors in the same lateral footprint without interfering with transistor operation, thereby reducing the effective area dedicated to power delivery while maintaining performance.
2Reliability
If power rails are increased in aspect ratio by making them deeper to reduce resistance, then power delivery performance is improved, but via resistance increases and BEOL capacitance increases
Solution Approach 1:
By moving power rails to the buried position underneath transistors, the patent enables aspect ratio increase in the vertical dimension without proportionally increasing via depth from the top surface. The power rails are accessed through backend metallization layers rather than requiring deep front-end vias, thus achieving low resistance without excessive via complexity.
3Productivity
If traditional 2D scaling is continued to increase transistor density, then transistor count per unit area increases, but return on investment decreases rapidly
Solution Approach 1:
The patent employs buried power rails that extend vertically underneath transistors, utilizing the third dimension to achieve higher transistor density without proportionally increasing manufacturing complexity. This 3D approach to power delivery enables continued scaling of transistor density while maintaining manufacturing efficiency by avoiding excessive lateral congestion and simplifying power rail routing.
Data Source
AI summary
Aspects of the disclosure provide a method for fabricating a semiconductor device. The method includes forming dummy power rails on a substrate by accessing from a first side of the substrate that is opposite to a second side of the substrate. Further, the method includes forming transistor devices and first wiring layers on the substrate by accessing the first side of the substrate. The dummy power rails are positioned below a level of the transistor devices on the first side of the substrate. Then, the method includes replacing the dummy power rails with conductive power rails by accessing from the second side of the substrate that is opposite to the first side of the substrate.