Buried Power Rail Transformers for Advanced Node Scaling
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Solution Overview
Problem
The scaling of transistors in advanced semiconductor technologies beyond the 5-nm node faces challenges due to severe design issues, including short-channel effects and increased wire/contact resistances, which are exacerbated by the limited performance of on-chip transformers caused by conductivity limitations and substrate losses, leading to increased die size and costs.
Innovation Solution
The integration of buried power rails (BPRs) and transformers with two electrically conductive layers, where the BPRs are buried within the substrate, and transformers are formed using lateral or vertical couplings between coils, optimizing conductivity and reducing substrate losses, thereby enhancing the Q-factor and coupling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional on-chip transformers are used, then power delivery is provided, but conductivity limitations and substrate losses degrade performance and increase die size
Solution Approach 1:
The patent moves the transformer from the conventional planar on-chip configuration to a three-dimensional structure utilizing buried power rails within the substrate. The transformer coils are formed in vertical trenches extending through the substrate depth, transforming a two-dimensional surface problem into a three-dimensional volume utilization solution. This dimensional transition enables improved magnetic coupling and reduced substrate losses while maintaining compact die footprint.
Solution Approach 2:
The transformer structure embeds multiple functional elements within the substrate volume. The buried power rails are nested within the substrate, with transformer coils formed in trenches that contain magnetic core materials. Signal lines and power rails are interleaved in alternating patterns, creating a nested configuration where multiple conductive elements occupy overlapping spatial regions, thereby maximizing space utilization and improving coupling efficiency.
2Productivity
If transistor scaling continues beyond 5-nm node, then device density increases, but short-channel effects and wire/contact resistances worsen
Solution Approach 1:
The patent addresses short-channel effects by transitioning from planar transistor gates to three-dimensional FinFET structures with vertical channels. The fins extend vertically from the substrate, creating multiple gate-controlled surfaces that improve channel control and reduce short-channel effects. This dimensional transition enables continued scaling while maintaining device performance.
Solution Approach 2:
The substrate is segmented into multiple functional regions with alternating signal and power rails, creating a fine-grained power delivery network. This segmentation allows localized power delivery to dense transistor regions, reducing voltage drops and IR losses that would otherwise limit further scaling. The interleaved configuration ensures that no transistor region is far from a power rail, maintaining reliability at high density.
3Reliability
If buried power rails are implemented, then conductivity is improved and substrate losses reduced, but manufacturing complexity increases
Solution Approach 1:
The buried power rails and transformer structures are formed during the early stages of substrate processing, before final device assembly. The trenches for transformer coils and the regions for buried rails are defined and filled with conductive and magnetic materials during the BEOL process. This preliminary formation simplifies subsequent steps, as the three-dimensional structures are already in place and serve as fixed reference features for later interconnect formation.
Solution Approach 2:
The buried power rail structure serves multiple functions simultaneously: it provides low-resistance power delivery, acts as a magnetic shield for the transformer, and forms part of the transformer coil structure itself. The alternating signal and power rails create both power delivery pathways and magnetic coupling structures. This multi-functionality reduces the need for separate dedicated structures, thereby simplifying the overall manufacturing process despite the three-dimensional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved performance of transformers by utilizing low ohmic conductors with good lateral alignment, reduces die size, and optimizes electrical features, allowing for superior power delivery and signal isolation while skipping ESD protection, thus addressing the scaling challenges and cost issues.
Implementation Method 1
transformers are formed using lateral or vertical couplings between coils, optimizing conductivity and reducing substrate losses, thereby enhancing the Q-factor and coupling efficiency
Data Source
AI summary
IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.