Self-Aligned Buried Power Rail for Non-Planar Transistor Scaling
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, and issues with source/drain contacts and gate electrodes shorting to power rails in non-planar transistor architectures.
Innovation Solution
The implementation of self-aligned buried power rails that connect source/drain regions, formed using a self-aligned process to mitigate shorting issues and enhance scaling, allowing for increased transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node and below
Solution Approach 1:
The power rail structure is formed preliminarily before the gate electrode deposition, establishing a self-aligned reference that guides subsequent gate positioning. This preliminary formation of the power rail with its specific geometry and position enables automatic alignment of the gate electrode, reducing variability in feature dimensions at advanced nodes
Solution Approach 2:
The power rail structure serves a dual function: it provides electrical power connection and simultaneously acts as a self-aligned mask and reference for gate electrode positioning. The structure serves itself to define the gate location, eliminating the need for separate alignment processes and reducing manufacturing variability
2Quantity of substance
If transistor dimensions are reduced to increase density, then quantity of devices increases, but reliability deteriorates due to shorting between source/drain contacts and gate electrodes
Solution Approach 1:
The power rail structure acts as an intermediary element between the source/drain contacts and the gate electrode, providing physical separation and electrical isolation. This intermediary structure prevents direct contact between the source/drain regions and gate electrode, eliminating shorting paths while enabling continued scaling for increased transistor density
3Quantity of substance
If multi-gate transistors are scaled down, then transistor density increases, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The power rail structure serves as a self-aligned reference that automatically defines the gate electrode position and dimensions. By forming the power rail first with precise geometry, subsequent gate formation uses this structure as a template, ensuring consistent dimensional control across multiple transistors and enabling high density without sacrificing precision
Data Source
AI summary
Embodiments include semiconductor devices. In an embodiment, a semiconductor device comprises a first non-planar transistor over a substrate and a second non-planar transistor over the substrate and parallel to the first non-planar transistor. In an embodiment, a gate structure is over the first non-planar transistor and the second non-planar transistor. In an embodiment, a power rail is between the first non-planar transistor and the second non-planar transistor. In an embodiment, a top surface of the power rail is below a top surface of a gate structure.