Buried Power Interconnect Layout for Scaled Semiconductor Contacts
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to high integration, leading to challenges in achieving improved performance and reliability.
Innovation Solution
The semiconductor device design includes a substrate with adjacent active patterns, source/drain patterns, active contacts, upper contacts, and buried lower power interconnection lines, which are strategically structured to enhance electrical characteristics and reliability through specific patterning and interconnection processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to improve integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The contact structure is divided into multiple segments: upper contact, lower contact portion, and buried interconnection portion. Each segment serves a specific function and can be independently optimized. The lower contact portion is further segmented into different width regions (first width, second width, third width) with different ratios to control electrical characteristics while maintaining compact integration.
Solution Approach 2:
The contact structure transitions from a simple planar contact to a three-dimensional multi-layer structure extending vertically through different substrate depths. The lower contact portion extends downward into the substrate, and the buried interconnection portion is positioned at a lower depth, creating vertical interconnection pathways that reduce lateral spacing requirements and improve integration density without compromising electrical performance.
2Ease of manufacture
If contact structure is simplified to reduce manufacturing complexity, then manufacturing ease improves, but electrical characteristics and reliability deteriorate
Solution Approach 1:
The dummy pattern is formed in advance during the patterning process, which later serves as a guide for forming the lower contact hole. This preliminary structuring enables self-alignment of the lower contact with the upper contact, eliminating the need for separate alignment processes and simplifying manufacturing while ensuring precise electrical connection.
Solution Approach 2:
The dummy pattern automatically serves dual purposes: as a placeholder during transistor formation and as an alignment reference for subsequent contact hole formation. The structure self-organizes to provide both mechanical support during fabrication and electrical connection pathways, reducing the number of separate manufacturing steps required.
Data Source
AI summary
A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.