Buried Vertical Rail Contact Layout for Low-Resistance Power Delivery
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Solution Overview
Problem
In semiconductor device manufacturing, defects occur during the depositing and etching processes for forming power delivery wirings on the back side of a base layer, leading to suboptimal electrical characteristics.
Innovation Solution
A semiconductor device design that includes a buried vertical rail with a metal pattern and barrier pattern, where the barrier pattern is controlled to minimize contact resistance and residue from re-sputtering, and the contact plug directly contacts the buried vertical rail, eliminating the need for a barrier pattern at the contact interface between the metal patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a barrier pattern is formed around the metal pattern during depositing and etching processes, then the metal wiring structure is protected and defined, but contact resistance increases and defects occur due to re-sputtering residue
Solution Approach 1:
The patent extracts and removes the barrier pattern from the contact region between the lower contact plug and the buried vertical rail. By selectively eliminating the barrier pattern only in the contact area while maintaining it in other wiring regions, the invention reduces contact resistance and prevents defects caused by re-sputtering residue, thereby improving electrical characteristics without compromising the overall wiring structure definition
Solution Approach 2:
The patent applies different structural qualities to different regions: the barrier pattern is present in the upper wiring regions for proper metal definition and protection, but intentionally absent in the contact region between the lower contact plug and buried vertical rail. This local differentiation allows the contact region to have low resistance while other regions maintain structural integrity
2Reliability
If the lower contact plug directly contacts the buried vertical rail without a barrier pattern, then contact resistance is reduced, but manufacturing complexity increases due to precise process control requirements
Solution Approach 1:
The patent performs preliminary formation of the lower contact plug structure before completing the barrier pattern deposition. The lower contact plug is formed first, then the barrier pattern is deposited but intentionally not formed in the contact region. This preliminary action allows precise control of the contact interface while simplifying the overall manufacturing process by avoiding complex post-processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical characteristics by reducing contact resistance and minimizing defects, resulting in improved performance and reliability of the semiconductor device.
Implementation Method 1
A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other
Data Source
AI summary
A semiconductor device includes a base layer including a silicon material. A field effect transistor is disposed on a first surface of the base layer. A first insulating interlayer covers the field effect transistor, A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern and a first barrier pattern surrounding a sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern and a second barrier pattern surrounding a sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.