Buried Rail Power Delivery in FinFET ICs for Reliable Transmission

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Solution Overview

Problem

Existing integrated circuit devices face challenges in reliably transmitting power due to the limitations of their power delivery networks, particularly in highly integrated circuits where power distribution efficiency is compromised.

Innovation Solution

The integrated circuit device incorporates a substrate with fin-type active regions, a device separation layer, source/drain regions, conductive plugs, power wiring lines, buried rails, and power vias to enhance power transmission efficiency, utilizing a layered structure with insulating barriers and conductive plugs to connect these components effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional power delivery networks are used in highly integrated circuit devices, then device integration is achieved, but power transmission reliability deteriorates

Engineering Contradiction:
Improvedevice integrationVSAvoidpower transmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a buried rail structure located beneath the substrate, creating a new dimensional pathway for power delivery. This subsurface power transmission path allows power to reach highly integrated regions without relying solely on surface-level wiring, thereby maintaining reliability as integration increases

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The buried rail acts as an intermediary power transmission element between the power supply and the highly integrated circuit regions. It mediates power delivery by providing a dedicated, low-resistance pathway that bypasses the limitations of conventional surface wiring, ensuring reliable power transmission despite high integration density

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If conventional power wiring is used, then device complexity is reduced, but power distribution efficiency deteriorates

Engineering Contradiction:
Improvepower delivery structureVSAvoidpower distribution efficiency
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The power delivery system is segmented into multiple functional components: power wiring lines on the surface, buried rails beneath the substrate, and via holes for vertical connection. This segmentation allows each component to be optimized for its specific function, with the buried rail providing a dedicated low-resistance path that improves power distribution efficiency without significantly increasing overall device complexity

Inventive Principle:
Principle #1Segmentation

3Area of stationary object

If power wiring lines are extended to reach all regions, then power coverage is improved, but resistance increases

Engineering Contradiction:
Improvepower coverage areaVSAvoidpower transmission
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

Instead of extending surface power wiring lines across the entire device area (which would increase resistance), the patent utilizes a subsurface dimension by placing buried rails beneath the substrate. This allows power to reach distant and highly integrated regions through a separate, optimized pathway that maintains low resistance while providing comprehensive power coverage

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12557680B2Integrated circuit device
Publication Date: 2026.02.17 SAMSUNG ELECTRONICS CO LTD
  • US12557680B2 patent drawing
  • US12557680B2 patent drawing
  • US12557680B2 patent drawing

AI summary

An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.