Buried Rail Semiconductor Device with Variable Width

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Solution Overview

Problem

Conventional semiconductor device fabrication processes for CMOS transistors are costly and inefficient, particularly when implementing buried power rails, which hinder the miniaturization and performance enhancement of semiconductor devices.

Innovation Solution

The semiconductor device incorporates buried rails with varying widths, utilizing a dummy fin process to reduce resistance and size, and employs an oval-shaped cross-section for the buried power rail to increase the cross-sectional area without sacrificing volume, thereby improving performance and reducing production costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication processes are used for CMOS transistors with buried power rails, then manufacturing precision can be maintained, but production cost increases and device miniaturization is hindered

Engineering Contradiction:
Improvemanufacturing precisionVSAvoidproduction cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The fabrication process is divided into two main segments: first forming transistors above the substrate, then separately forming the buried rails within the substrate. This segmentation allows each component to be optimized independently, reducing overall manufacturing complexity and cost while maintaining precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buried rails are formed by extending conductive regions vertically into the substrate, adding a depth dimension to the rail structure. This vertical extension increases the effective cross-sectional area of the rails without increasing their planar footprint, thereby reducing resistance without requiring larger device area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If buried power rails are implemented using conventional methods, then device functionality is maintained, but device size increases and performance is limited

Engineering Contradiction:
Improvedevice functionalityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The rail structure utilizes the vertical dimension by extending conductive regions into the substrate, creating a three-dimensional rail geometry. This allows the rails to achieve lower resistance through increased effective cross-sectional area without proportionally increasing the device's planar area or overall volume

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The buried rails are nested within the substrate volume, with conductive regions positioned at different depths. This nested arrangement allows multiple rail segments to occupy overlapping horizontal spaces at different vertical levels, maximizing space utilization and reducing the device footprint

Inventive Principle:
Principle #7Nested doll (Nesting)

3Ease of manufacture

If standard width buried rails are used, then fabrication simplicity is maintained, but resistance within the rails increases

Engineering Contradiction:
Improvefabrication simplicityVSAvoidrail resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The rail structure implements variable cross-sectional dimensions where the vertical depth of conductive regions varies at different horizontal positions. This creates locally optimized rail geometry with larger cross-sectional area in regions requiring lower resistance, while maintaining simpler geometry in other areas

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The rail cross-sectional parameters are changed by varying the depth and width of conductive regions at different locations. This allows optimization of electrical resistance by increasing the effective cross-sectional area without uniformly increasing all dimensions, thereby maintaining fabrication simplicity while improving electrical performance

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11393819B2Semiconductor device implemented with buried rails
Publication Date: 2022.07.19 QUALCOMM INC
  • US11393819B2 patent drawing
  • US11393819B2 patent drawing
  • US11393819B2 patent drawing

AI summary

Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.