Buried Sacrificial Structures for Wafer-Level Die Singulation
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Solution Overview
Problem
Current wafer-level die singulation methods, such as mechanical sawing and laser sawing, result in wasted chip area, potential damage to dies, and increased process complexity, especially for advanced technology nodes, and do not allow for non-standard die shapes or dense packing.
Innovation Solution
A method involving the use of buried sacrificial structures embedded in the wafer substrate to separate individual dies through etching, eliminating the need for scribe lines and enabling ultra-small thickness and non-standard die shapes with improved design flexibility and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mechanical sawing or laser sawing is used for wafer-level die singulation, then dies can be separated from the wafer, but chip area is wasted due to scribe lines and dies may be damaged
Solution Approach 1:
The patent performs preliminary action by forming buried sacrificial structures at designated separation locations before completing die fabrication. These sacrificial structures are embedded in the wafer substrate and positioned where scribe lines would traditionally be required. After dies are formed and processed, the sacrificial structures are removed to enable die release, thereby eliminating the need for wide scribe lines and maximizing chip area utilization.
Solution Approach 2:
The patent applies the extraction principle by removing the sacrificial structures after they have served their purpose as separation guides during fabrication. The sacrificial structures are selectively removed through etching or other removal processes, creating voids that allow dies to be released from the wafer substrate without requiring traditional mechanical sawing paths, thus eliminating waste of chip area.
2Productivity
If mechanical sawing is used for die separation, then dies can be singulated, but process complexity increases due to backside grinding requirements
Solution Approach 1:
The patent replaces the mechanical sawing system with a chemical etching system. Instead of using mechanical blades to cut through the wafer and requiring subsequent backside grinding to remove saw marks, the invention uses selectively removable sacrificial structures that are chemically etched away. This substitution eliminates the need for mechanical intervention and associated post-processing steps like backside grinding, thereby reducing overall process complexity.
3Productivity
If traditional singulation methods are used, then dies can be separated, but non-standard die shapes and dense packing are not enabled
Solution Approach 1:
The patent applies local quality by forming sacrificial structures with specific local geometries that match the desired die shapes and separation requirements. Rather than using uniform scribe lines, the sacrificial structures can be patterned to accommodate non-standard die shapes, irregular layouts, and dense packing configurations. This localized customization of the sacrificial structure geometry enables versatile die designs while maintaining the benefits of the sacrificial structure approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances chip area utilization, reduces die damage, and allows for dense packing of non-standard shapes, increasing productivity and yield without the need for additional processing steps like backside grinding.
Implementation Method 1
separate the individual dies from the wafer substrate by removing the buried sacrificial structures
Data Source
AI summary
Semiconductor wafers and methods of fabricating the same are provided. An example semiconductor wafer has multiple die regions separated by a die spacing region and includes a wafer substrate, multiple dies disposed over the wafer substrate, and multiple buried sacrificial structures corresponding to the multiple dies. Each die is located in the corresponding die region and further includes a die substrate, an integrated circuit (IC) device disposed in the die substrate, and a multi-layer interconnect structure disposed on the IC device. The buried sacrificial structure is surrounding the die substrate and disposed between the die and the wafer substrate. The buried sacrificial structure further includes a bottom portion disposed in the die region and a side portion circumferentially connected to the bottom portion. The side portion is located in the die spacing region surrounding the corresponding die and disposed on the sidewall of the die substrate.