Buried Semiconductor Element in Dual-Sided Wiring Board
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Solution Overview
Problem
Semiconductor devices with buried elements face challenges in reducing thickness and pitch due to asymmetric thermal expansion and lack of flexibility in mounting external components, particularly in package-on-package structures, due to the reliance on conductive bumps and limited terminal arrangements.
Innovation Solution
A semiconductor device with a semiconductor element buried in a wiring board, where insulating and wiring layers are formed on both surfaces, allowing direct via connections between layers and enabling symmetric thermal expansion, and external terminals are provided on both sides for enhanced mounting flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conductive bumps are used to connect semiconductor element and substrate, then electrical connection is achieved, but pitch cannot be reduced and device thickness increases
Solution Approach 1:
The patent removes the conductive bumps from the connection structure. Instead of using bumps to connect the semiconductor element to the substrate, the invention uses direct wiring layers that extend from the element terminals through the substrate to the other side, eliminating the need for separate bump connectors and thereby reducing both pitch and thickness constraints
Solution Approach 2:
The patent transitions from a vertical connection approach (using bumps that extend upward from the substrate surface) to a horizontal/directional connection approach where wiring layers pass through the substrate from one side to the other, enabling finer pitch and reduced overall device thickness
2Reliability
If semiconductor element is surface-mounted on substrate, then electrical connection is achieved, but device thickness increases by bump diameter and handling strength requirements increase
Solution Approach 1:
Instead of mounting the semiconductor element on the substrate surface with connections extending upward, the patent inverts the approach by having the wiring layers pass through the substrate from the element side to the opposite side, allowing the element to be positioned within or near the substrate rather than mounted on its surface
3Length of stationary object
If coreless substrate structure is used, then thickness is reduced, but asymmetric thermal expansion causes substrate warp
Solution Approach 1:
The patent intentionally creates a symmetric structure by forming wiring layers and insulating layers on both the front and back surfaces of the substrate. This symmetry in layer distribution compensates for the asymmetric thermal expansion coefficients of different materials, preventing substrate warp while maintaining reduced thickness
4Ease of manufacture
If asymmetric layer structure is used in coreless substrate, then manufacturing is simplified, but thermal expansion asymmetry causes warp
Solution Approach 1:
The patent applies asymmetric layer formation on each individual surface (front and back) while maintaining overall symmetry in the complete structure. This approach simplifies manufacturing by using standard build-up processes on each surface while the combined symmetric configuration prevents thermal expansion-induced warp
Data Source
AI summary
A semiconductor device includes a semiconductor element having a first surface on which an electrode terminal is formed, and a second surface located opposite to the first surface. The semiconductor device further includes a first insulating layer in which the semiconductor element is buried, and second insulating layers and wiring layers formed in such a manner that at least one insulating layer and at least one wiring layer are formed on each of both surfaces of the first insulating layer. The electrode terminal of the semiconductor element is connected to a first wiring layer located on the first surface side through a first via formed in the first insulating layer, and the first wiring layer is connected to a second wiring layer located on the second surface side through a second via formed in the first insulating layer.