Buried Semiconductor Layer for Pinned Photodiode Charge Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional solid-state imaging devices face challenges in increasing storage capacity and reducing noise for larger pixel sizes, particularly with pinned photodiodes, where the accumulated charge is limited to pn-junction capacitance near the surface, leading to inefficient charge storage and deteriorated conversion efficiency.
Innovation Solution
The solid-state imaging device incorporates a substrate with a buried first conductivity type semiconductor layer and a second conductivity type separation layer, featuring sub-areas perpendicular to the substrate, which enhances junction capacitance and allows for efficient charge transfer using a single charge transfer gate, thereby increasing storage capacity and sensitivity while reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pixel size is increased to improve light reception area, then the storage capacity should increase, but the charge storage is limited to pn-junction capacitance near the surface which deteriorates conversion efficiency
Solution Approach 1:
The patent extends the charge storage region from the surface level into the depth direction by forming an n-type semiconductor layer that penetrates from the light-receiving surface toward the opposite surface. This vertical extension into the third dimension (depth) allows the charge storage capacity to scale with pixel size without being constrained by surface-area-dependent pn-junction capacitance, thereby maintaining conversion efficiency while increasing storage capacity.
2Device complexity
If the accumulated charge is limited to pn-junction capacitance near the surface, then the device structure remains simple, but the storage capacity is insufficient for larger pixels
Solution Approach 1:
The patent forms an n-type semiconductor layer that extends vertically through the substrate depth, creating a three-dimensional charge storage region. This vertical dimensionality change allows the storage capacity to increase proportionally with pixel size and layer depth, providing sufficient charge storage for larger pixels without requiring complex multi-layer or distributed storage structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases storage capacity, reduces noise, and enhances sensitivity, allowing for a wider dynamic range without degrading optical characteristics, enabling efficient charge transfer and improved image quality.
Implementation Method 1
a first conductivity type semiconductor layer which is formed so as to be buried in the substrate and has a photoelectric conversion function for received light and a charge accumulation function
Implementation Method 2
having a junction capacitance component together with the first conductivity type semiconductor layer
Data Source
AI summary
A pinned photodiode has a substrate having a first substrate side to which light is illuminated and a second substrate side opposite the first substrate side, a photoelectric conversion part including a first conductivity type semiconductor layer buried into the substrate and having a photoelectric conversion function for the received light and a charge accumulation function, a second conductivity type separation layer formed in the side portion of the first conductivity type semiconductor layer in the photoelectric conversion part, and one charge transfer gate part capable of transferring the charge accumulated in the photoelectric conversion part. The photoelectric conversion part, in at least a portion of the first conductivity type semiconductor layer, includes at least one second-conductivity type semiconductor layer forming at least one sub-area in a direction perpendicular to a normal line of the substrate and having a junction capacitance component together with the first conductivity type semiconductor layer.