Buried Semiconductor Marking Structure for Chip Authentication

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Solution Overview

Problem

Current methods for authenticating integrated circuits, such as visible logos and serial numbers, are easily reproducible, leading to concerns about the reliability and confidence in the quality of cloned chips, which can negatively impact sales.

Innovation Solution

A method for manufacturing a marked single-crystalline substrate with a buried structured semiconductor layer using a first semiconductor material under a second semiconductor material, where the lattice mismatch is less than 10%, creating an invisible marking that can only be detected under specific conditions, such as x-rays, to prevent falsified clones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If visible logos and serial numbers are placed on chips for authentication, then tracking and identification capability is improved, but ease of reproduction by unauthorized companies increases

Engineering Contradiction:
Improveauthentication capabilityVSAvoidease of reproduction
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The marking structure is extracted from the visible surface and embedded within the semiconductor substrate. The marking is formed in a first semiconductor layer that is subsequently covered by a second semiconductor layer, removing the marking from public view while maintaining its authentication function within the device structure.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The authentication marking transitions from a two-dimensional surface feature to a three-dimensional embedded structure. By placing the marking inside the substrate and covering it with additional layers, the marking moves to a different spatial dimension that is not accessible during normal device operation or replication.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If a buried marking structure with lattice mismatch less than 10% is used, then resistance to falsification is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveauthenticity verificationVSAvoidlattice matching precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent specifies a quantitative parameter threshold for lattice mismatch (less than 10%) that balances authentication reliability with manufacturing feasibility. This parameter change transforms an abstract quality requirement into a measurable specification that guides material selection and process control.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The buried marking structure effectively prevents the reproduction of authentic marks, ensuring the reliability and authenticity of semiconductor devices, thereby maintaining customer confidence and preventing fraud.

Implementation Method 1

the lattice mismatch of the first and second semiconductor materials is less than 10% (or less than 6%), i.e. the difference of the lattice constants of the first and second semiconductor materials is less than 10% (or less than 6%)

Methodology Applied
Scientific EffectLattice mismatch:

Data Source

PatentUS9048244B2Method for manufacturing a marked single-crystalline substrate and semiconductor device with marking
Publication Date: 2015.06.02 INFINEON TECHNOLOGIES AG
  • US9048244B2 patent drawing
  • US9048244B2 patent drawing
  • US9048244B2 patent drawing

AI summary

A method for manufacturing a marked single-crystalline substrate comprises providing a single-crystalline substrate comprising a first material, the single-crystalline substrate having a surface area; forming a marking structure on the surface area of the single-crystalline substrate, wherein the marking structure comprises a first semiconductor material; and depositing a semiconductor layer on the marking structure and at least partially on the surface area of the single-crystalline substrate, wherein the semiconductor layer comprises the second semiconductor material, and wherein the marking structure is buried under the second semiconductor material.