Buried Shield Structure for Flash Memory Isolation
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Solution Overview
Problem
Conventional flash memory devices face electrical insulation breakdown and punch-through leakage issues due to differences in dimensions between isolation layers, leading to deteriorated electrical characteristics and operational inefficiencies during reading and erasing operations.
Innovation Solution
A semiconductor device with a buried shield structure is introduced, featuring a polysilicon or metal compound-based pattern sequence on an isolation layer between cell and high voltage transistor areas, along with sidewall spacers and specific dielectric layers, to enhance electrical insulation and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation layers are made deeper to ensure electrical insulation between cell transistor and high voltage transistor, then electrical insulation is improved, but manufacturing complexity increases and device size increases
Solution Approach 1:
The isolation structure is divided into two distinct layers: a first isolation layer (shallow) for isolating cell transistors and a second isolation layer (deep) for isolating high voltage transistors. This segmentation allows each layer to be optimized for its specific function, with the deep second isolation layer providing the necessary electrical insulation for high voltage transistors without requiring the entire isolation structure to be uniformly deep, thus reducing manufacturing complexity
Solution Approach 2:
Different isolation depths are applied to different regions of the device. The second isolation layer is formed deeper only in the high voltage transistor area where electrical insulation is critical, while the first isolation layer suffices for cell transistor areas. This local differentiation of isolation depth provides necessary insulation where needed without unnecessarily increasing device size or manufacturing complexity across the entire chip
2Reliability
If second isolation layer is made larger in width and depth to ensure electrical insulation, then electrical insulation is improved, but device size increases
Solution Approach 1:
The second isolation layer is configured with larger width and depth specifically in the high voltage transistor area where electrical insulation is critical, while maintaining smaller dimensions in other areas. This localized sizing ensures adequate insulation for high voltage operations without unnecessarily increasing the overall device footprint
3Reliability
If first and second isolation layers have considerably different dimensions, then electrical insulation for high voltage transistors is improved, but manufacturing process complexity increases
Solution Approach 1:
The isolation structure is divided into two distinct layers formed through separate manufacturing processes. The first isolation layer is formed to a shallower depth suitable for cell transistor isolation, while the second isolation layer is formed deeper in the high voltage transistor area. This segmentation into discrete formation steps makes the manufacturing of differently dimensioned isolation layers more manageable and less complex than attempting to form a single uniform isolation structure
4Adaptability or versatility
If high voltage transistors are used in the flash memory device, then high operation voltage capability is achieved, but electrical insulation breakdown and punch-through leakage occur
Solution Approach 1:
The second isolation layer is specifically configured with greater depth and width in the high voltage transistor area, providing enhanced local electrical insulation where high voltage stress is applied. This localized reinforcement of isolation structure prevents electrical insulation breakdown and punch-through leakage in the high voltage transistor region while maintaining overall device functionality
Data Source
AI summary
A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.