Buried Silicide Local Interconnect via Sidewall Spacers
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Solution Overview
Problem
Conventional methods for forming local interconnects in semiconductor devices using doped polysilicon face routing restrictions, particularly when trying to cross regions with transistor gates, and result in substrate cluttering and increased processing complexity.
Innovation Solution
The method involves etching a recess into a substrate with sidewall spacers, forming silicide at the bottom, and filling with metal to create a buried local interconnect, which reduces the size of the interconnect and minimizes substrate clutter by using counterdoping and dielectric spacers to isolate the interconnect region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped polysilicon is used as local interconnect material, then thermal budgeting and gate material compatibility are improved, but routing flexibility deteriorates due to inability to cross transistor gate regions
Solution Approach 1:
The patent moves the local interconnect from the surface level to a buried position within recesses in the substrate. By etching recesses into the substrate and forming silicide interconnects at the bottom, the interconnect is placed in a different spatial dimension (below the surface), allowing it to cross under transistor gate regions without electrical contact, thus resolving the routing flexibility limitation while maintaining compatibility with the existing polysilicon gate structure.
2Ease of manufacture
If conventional lithographic and etching techniques are used to form local interconnects, then manufacturing simplicity is maintained, but minimum feature size is limited preventing further scaling
Solution Approach 1:
The patent employs self-aligned fabrication techniques where sidewall spacers are formed on the recess walls, and the silicide is deposited only in the recess bottom area defined by these spacers. This self-alignment mechanism automatically defines the interconnect dimensions without requiring additional lithographic patterning steps, enabling sub-lithographic feature sizes while maintaining manufacturing simplicity. The spacer width directly controls the interconnect dimensions, achieving scaling below the lithographic resolution limit.
3Ease of manufacture
If local interconnect layers are deposited at the silicon-silicon dioxide interface, then conventional processing is maintained, but substrate area cluttering increases
Solution Approach 1:
The patent transitions from surface-level interconnect deposition to buried interconnect formation by etching recesses into the substrate and depositing silicide at the bottom of these recesses. This vertical relocation of the interconnect to a subsurface position eliminates the need for surface area, allowing the interconnect to be embedded within the substrate volume. Consequently, the substrate surface remains clear for other structures, improving area utilization while maintaining compatibility with conventional semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for smaller, more efficient local interconnects, enabling further scaling down of cell size and reducing chip area usage while maintaining low resistance and reducing substrate clutter.
Implementation Method 1
A metal is deposited in the recess and the metal in the recess is reacted to form silicide at the bottom of the recess
Data Source
AI summary
A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.