Buried Skip Vias for PCB Signal Integrity
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Solution Overview
Problem
Current printed circuit board (PCB) fabrication techniques face challenges in achieving improved signal and power integrity, particularly in reducing the number of lamination cycles required, which affects fabrication efficiency and costs.
Innovation Solution
The implementation of buried skip vias in a high-density interconnect (HDI) based PCB design, where vias are formed between specific layers to bypass one or more layers, reducing the number of lamination cycles needed while enhancing signal and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional via formation methods are used to connect conductive layers, then electrical connections are achieved, but the number of lamination cycles increases and fabrication complexity increases
Solution Approach 1:
The via connection path is segmented into two separate operations: first forming a recess in the insulating layer, then forming the via hole within that recess. This segmentation allows the via to connect to the conductive layer without requiring the via to traverse through multiple insulating layers, thereby reducing the number of lamination cycles needed while maintaining electrical connection reliability
Solution Approach 2:
The via hole is positioned at an angle relative to the conductive layer rather than being perpendicular, creating a skip via structure that connects to the conductive layer from a different spatial dimension. This angular positioning reduces the depth the via must traverse through insulating layers, decreasing lamination cycle requirements while preserving signal and power integrity
2Reliability
If traditional via formation methods are used to connect conductive layers, then electrical connections are achieved, but fabrication time and costs increase
Solution Approach 1:
A recess is formed in the insulating layer before the via hole is formed. This preliminary action creates a pre-positioned connection point that allows the via to be formed more quickly and with fewer subsequent lamination cycles, thereby improving fabrication efficiency while maintaining reliable electrical connections for signal and power integrity
Solution Approach 2:
The via hole is formed to skip over one or more insulating layers and connect directly to the conductive layer, bypassing the need to traverse through all intermediate layers. This skipping approach reduces the total number of lamination cycles required, thereby improving fabrication efficiency and reducing costs while maintaining connection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity of the lamination process, achieves improved signal and power integrity, and decreases the number of lamination cycles required, thereby increasing fabrication efficiency and reducing costs.
Implementation Method 1
a via can be formed by forming a hole that traverses through at least two adjacent conductive layers, and plating the hole with a conductive material that forms an electrical connection
Data Source
AI summary
A printed circuit board (PCB) includes an exterior section having a first set of layers including an outermost conductive layer. The PB further includes an interior section, adjacent to the exterior section, having a second set of layers including a first conductive layer corresponding to a first end of the interior section, a second conductive layer corresponding to a second end of the interior section opposite the first end, and a third conductive layer disposed between the first conductive layer and the second conductive layer. The exterior section further includes a set of vias extending from an outermost conductive layer to the first conductive layer. The interior section further includes a buried skip via extending from the first conductive layer to the third conductive layer.