Buried High-Resistivity SOI Structure With Interface Charge Trapping
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Solution Overview
Problem
High resistivity semiconductor-on-insulator wafers used for RF devices face issues with charge inversion or accumulation layers at the buried oxide interface, leading to parasitic power losses and device nonlinearity, which existing methods fail to adequately address.
Innovation Solution
A multilayer structure is developed with a high resistivity single crystal semiconductor layer having a roughened surface and an interfacial charge trapping layer of polycrystalline silicon, which traps charges to maintain substrate resistivity and improve RF performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistivity semiconductor-on-insulator wafer is used for RF devices, then the substrate resistivity is improved, but charge inversion or accumulation layers form at the buried oxide interface causing parasitic power losses and device nonlinearity
Solution Approach 1:
An intermediate layer is introduced between the high resistivity semiconductor substrate and the buried oxide layer. This intermediate layer acts as a mediator that prevents charge inversion or accumulation at the interface, thereby eliminating parasitic power losses and device nonlinearity while preserving the high substrate resistivity required for RF device performance
Solution Approach 2:
The invention converts the potentially harmful charge accumulation phenomenon into a beneficial effect by controlling and utilizing the charge distribution in the intermediate layer. The charge that would otherwise form harmful inversion or accumulation layers at the oxide interface is instead managed within the intermediate layer, transforming a reliability issue into a performance-enhancing feature
2Object-generated harmful factors
If existing methods are used to address charge inversion layers, then some mitigation is achieved, but parasitic power losses and device nonlinearity are not adequately reduced
Solution Approach 1:
The intermediate layer serves as an effective intermediary that physically separates the semiconductor substrate from the buried oxide, preventing the formation of charge inversion layers at their interface. This structural intervention directly addresses the root cause of parasitic power losses without requiring complex external mitigation techniques
Solution Approach 2:
The invention changes the physical and electrical parameters at the substrate-oxide interface by introducing the intermediate layer with specific material properties. This parameter change fundamentally alters the charge distribution and electrical characteristics at the interface, thereby reducing parasitic power losses and improving device linearity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively scatters charge carriers, reducing parasitic conduction and enhancing RF device performance by maintaining high resistivity even in the near-surface region, while being cost-effective and stable against defects.
Implementation Method 1
an interfacial charge trapping layer of polycrystalline silicon, which traps charges to maintain substrate resistivity
Implementation Method 2
The structure effectively scatters charge carriers, reducing parasitic conduction
Data Source
AI summary
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).