Buried and Surface Wiring Patterns for High-Density PCB
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Solution Overview
Problem
The increasing demand for high-density input/output (I/O) counters in semiconductor devices necessitates a printed circuit board with enhanced wiring density, while maintaining the same number of layers and size, to accommodate multiple I/Os effectively.
Innovation Solution
The design incorporates a layered structure with a first insulating layer, a first wiring layer buried within it, and a second wiring layer on the surface, where the second wiring patterns are spaced apart from the first and overlap each other, allowing for additional wiring without increasing the substrate's layers or size, and includes via layers for connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers of substrate or size of substrate is increased to accommodate more wiring patterns, then wiring density is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from traditional planar wiring layout to a three-dimensional stacked configuration where wiring patterns are arranged in multiple layers vertically. Specifically, first wiring patterns are formed on a substrate, insulating layers are deposited, and second wiring patterns are formed on top, creating a vertical stacking architecture that increases wiring capacity without expanding the horizontal footprint.
Solution Approach 2:
The patent implements a nested structure where multiple wiring patterns are embedded within insulating layers in a hierarchical arrangement. The first wiring patterns are embedded in the substrate, covered by insulating layers, with second wiring patterns formed above them, creating a nested configuration that maximizes space utilization and wiring density within the same footprint.
2Quantity of substance
If the number of layers of substrate or size of substrate is increased to accommodate more wiring patterns, then wiring density is improved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from traditional planar wiring layout to a three-dimensional stacked configuration where wiring patterns are arranged in multiple layers vertically. Specifically, first wiring patterns are formed on a substrate, insulating layers are deposited, and second wiring patterns are formed on top, creating a vertical stacking architecture that increases wiring capacity without expanding the horizontal footprint.
Solution Approach 2:
The patent divides the wiring structure into distinct segments: first wiring patterns on the substrate, insulating layers in between, and second wiring patterns on top. This segmentation allows for modular manufacturing processes where each layer can be formed and processed independently, simplifying the overall manufacturing complexity despite the increased wiring density.
3Adaptability or versatility
If additional wiring patterns are added to increase I/O capacity, then functionality is improved, but signal interference between adjacent wiring patterns increases
Solution Approach 1:
The patent introduces insulating layers as intermediary structures between the first wiring patterns and second wiring patterns. These insulating layers act as mediators that electrically isolate adjacent wiring patterns, preventing signal interference and crosstalk while allowing the wiring patterns to be in close proximity, thereby maintaining high I/O capacity without harmful electromagnetic interference.
Solution Approach 2:
The patent transitions from traditional planar wiring layout to a three-dimensional stacked configuration where wiring patterns are arranged in multiple layers vertically. Specifically, first wiring patterns are formed on a substrate, insulating layers are deposited, and second wiring patterns are formed on top, creating a vertical stacking architecture that increases wiring capacity without expanding the horizontal footprint.
Data Source
AI summary
A printed circuit board includes a first insulating layer; a first wiring layer buried in the first insulating layer, exposed to one surface of the first insulating layer, and including a plurality of first wiring patterns; a second wiring layer including a plurality of second wiring patterns spaced apart from the plurality of first wiring patterns on the one surface of the first insulating layer; and a second insulating layer disposed on the one surface of the first insulating layer and covering the plurality of second wiring layers. At least a portion of the plurality of second wiring patterns on the one surface of the first insulating layer is disposed in regions between adjacent first wiring patterns among the plurality of first wiring patterns.