Buried Threshold Voltage Adjustment Layer in High-k Gate Stacks
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Solution Overview
Problem
Existing semiconductor devices with high-k gate stacks face challenges in achieving desired threshold voltages for N-MOS and P-MOS transistors due to ineffective work function control, requiring thick threshold voltage adjustment layers that are prone to depletion and high-temperature processing, which can lead to defects and low carrier mobility.
Innovation Solution
A buried threshold voltage adjustment layer is interposed between two high-k films in the gate stack, allowing for controlled diffusion and reduced heat treatment temperatures, minimizing layer thickness and maintaining high mobility while achieving desired threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick threshold voltage adjustment layer is used to achieve desired threshold voltages, then the threshold voltage control is improved, but the layer becomes prone to depletion and requires high-temperature processing which causes defects and low carrier mobility
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a first high-k film, a thin threshold voltage adjustment layer, and a second high-k film. This segmentation allows the threshold voltage adjustment layer to be kept thin (avoiding depletion) while still achieving the desired threshold voltage control through the combined structure, eliminating the need for thick adjustment layers that cause reliability issues.
Solution Approach 2:
The patent uses a composite gate stack structure combining different materials (first high-k film, threshold voltage adjustment layer, second high-k film) to achieve functionality that cannot be obtained with a single material. The composite structure provides both threshold voltage control and maintains high carrier mobility by keeping the adjustment layer thin while using high-k materials to provide the necessary electrical characteristics.
2Manufacturing precision
If high-temperature processing is used to process thick adjustment layers, then the threshold voltage adjustment is achieved, but defects increase and carrier mobility decreases
Solution Approach 1:
The patent changes the thickness parameter of the threshold voltage adjustment layer from thick to thin, which fundamentally alters the processing requirements. Thin layers can be processed at lower temperatures, avoiding the defects and carrier mobility degradation associated with high-temperature processing of thick layers, while still achieving the necessary threshold voltage adjustment.
3Reliability
If the threshold voltage adjustment layer is made thin to maintain high mobility, then carrier mobility is improved, but the ability to achieve desired threshold voltages is reduced
Solution Approach 1:
The composite gate stack structure combines a thin threshold voltage adjustment layer with first and second high-k films. The high-k films have high dielectric constants that enhance the electrical field, allowing the thin adjustment layer to achieve sufficient threshold voltage control without being thick enough to cause depletion or reduce carrier mobility.
Solution Approach 2:
By segmenting the gate stack into multiple layers with different functions, the patent allows the threshold voltage adjustment layer to be optimized for thinness (maintaining mobility) while the combined structure of all layers provides the necessary threshold voltage control capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively controls the work function and threshold voltages of semiconductor devices, reducing the need for thick adjustment layers and high-temperature processing, thereby enhancing device performance and reliability.
Implementation Method 1
diffusion of chemical species throughout a gate stack during post-processing can affect the work function
Implementation Method 2
depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film
Data Source
AI summary
A method is provided for forming a semiconductor device containing a buried threshold voltage adjustment layer. The method includes providing a substrate containing an interface layer, depositing a first high-k film on the interface layer, depositing a threshold voltage adjustment layer on the first high-k film, and depositing a second high-k film on the threshold voltage adjustment layer such that the threshold voltage adjustment layer is interposed between the first and second high-k films. The semiconductor device containing a patterned gate stack is described.