Buried Track Formation for Semiconductor Interconnect Area Reduction
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Solution Overview
Problem
The interconnects formed during the Back-End-Of-Line phase in electronic device manufacturing are highly area-consuming, particularly the conductive track levels closest to the substrate, which poses a challenge in reducing space usage.
Innovation Solution
A method of manufacturing buried tracks by forming a cavity in a semiconductor layer, filling it with a conductive or semiconductor material, and partially removing the material from the upper portion to create the track, which can be used to connect electronic components without the need for thick conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick conductive track levels (M1, M2, M3) and conductive vias are used to form interconnects, then electrical connectivity between components is achieved, but the area consumption increases significantly
Solution Approach 1:
The patent extracts the conductive material from the upper portion of the cavity, removing only the necessary amount to create the track while leaving the lower portion filled. This extraction approach creates buried tracks that provide electrical connectivity without requiring thick conductive layers and vias, thereby reducing area consumption while maintaining connectivity reliability
Solution Approach 2:
The patent transitions from traditional planar interconnects to three-dimensional buried tracks formed within cavities in the substrate. By utilizing the vertical dimension and forming tracks at different depths within the substrate, the patent achieves electrical connectivity without occupying additional lateral space, thus resolving the area consumption issue
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of buried electric links, saving space typically used for conductive vias and enabling local connections between components without the need for conductive track levels M1, M2, and M3, thereby optimizing space utilization.
Implementation Method 1
step g) of filling of the cavity with the material of the first layer. According to an embodiment, step g) comprises, in the cavity, an epitaxial growth of the material of the first layer
Implementation Method 2
step e) of removal of the portion of the second layer located on the bottom of the cavity. According to an embodiment, step e) is an anisotropic etching of the material of the second layer
Data Source
AI summary
The present description concerns a method of forming a track in a first layer, including a) forming a cavity in the first layer; b) totally filling the cavity with a first material; and c) partially removing the first material from the upper portion of the cavity, to form the track made of the first material.