Buried Trench Capacitor Layout for EMI Reduction Without Area Penalty
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Solution Overview
Problem
Existing microelectronic devices face challenges in reducing electromagnetic interference (EMI) and silicon area usage due to the integration of bypass capacitors, which can be improved by incorporating buried trench capacitors within the device structure.
Innovation Solution
The integration of a buried trench capacitor below the top surface of the microelectronic device, formed between a silicon oxide capped polysilicon region and a deep well region, or between a polysilicon region and a silicon epitaxial region, with a trench liner dielectric, providing terminals through the substrate and well contacts for effective capacitance and reduced EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If bypass capacitors are integrated into the same chip as the microelectronic device, then electromagnetic interference (EMI) is improved, but silicon area usage increases
Solution Approach 1:
The patent moves the capacitor from the traditional planar surface of the chip into the vertical dimension by creating a buried trench structure that extends below the surface. This three-dimensional integration allows the capacitor to occupy subsurface volume rather than surface area, thereby reducing the silicon footprint while maintaining EMI filtering functionality.
Solution Approach 2:
The capacitor structure is nested within the substrate by forming a trench that extends into the silicon and filling it with capacitive elements. The capacitor is effectively embedded or nested within the existing substrate structure, allowing integration without proportionally increasing the overall device area.
2Area of stationary object
If bypass capacitors are placed on separate chips, then silicon area usage is reduced, but electromagnetic interference (EMI) increases
Solution Approach 1:
The patent merges the capacitor functionality with the main microelectronic device by integrating the buried trench capacitor directly into the substrate. This consolidation creates a unified structure where the capacitor and active devices share the same silicon substrate, providing EMI filtering close to the noise sources while maintaining compact area usage.
3Area of stationary object
If buried trench capacitors are formed below the top surface, then silicon area usage is optimized, but device complexity increases
Solution Approach 1:
The capacitor structure is segmented into distinct functional layers including the trench liner dielectric, the capacitive fill material (such as doped polysilicon), and the surrounding substrate regions. This segmentation allows each layer to be formed through specialized processing steps that are then integrated into the overall device fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances EMI reduction and optimizes silicon area usage by physically locating the capacitors below the electrical components, thereby improving the performance and efficiency of microelectronic devices.
Implementation Method 1
separated by a buried trench capacitor liner dielectric
Implementation Method 2
buried trench capacitor
Data Source
AI summary
A microelectronic device includes a buried trench capacitor below an electronic component of the microelectronic device. In one embodiment, the buried trench capacitor may be formed between a silicon oxide capped p-type buried trench capacitor polysilicon region and a buried trench capacitor deep n-type region separated by buried trench capacitor liner dielectric. In a second embodiment, the buried trench capacitor may be formed by a buried trench capacitor polysilicon region and a p-type silicon epitaxial region separated by a buried trench capacitor liner dielectric. One terminal of the deep trench capacitor is made through the substrate via a deep trench substrate contact. The second terminal of the deep trench capacitor is made via a well contact that connects to the capacitor through a deep well region in one embodiment and through a polysilicon layer in a second embodiment.