Buried Variable Resistance Layer in Semiconductor Memory
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in preventing changes in the characteristics of variable resistance layers during fabrication, which can lead to reliability issues and increased complexity in the manufacturing process.
Innovation Solution
The proposed solution involves forming a semiconductor memory device with a variable resistance layer positioned at the intersection of electrodes and buried within them, eliminating the need for an additional etch process for patterning, thereby preventing damage and maintaining the integrity of the variable resistance layer characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an additional etch process is used for patterning the variable resistance layer, then the manufacturing precision can be improved, but the device complexity and reliability worsen due to potential damage to the variable resistance layer characteristics
Solution Approach 1:
The variable resistance layer is formed to protrude above the electrode surface before the etch process is applied. This preliminary positioning ensures that the etch process only removes excess material above the electrode plane without damaging the variable resistance layer itself, thus maintaining both patterning precision and layer integrity
Solution Approach 2:
The variable resistance layer is divided into two parts: a protruding portion that extends above the electrode surface for precise patterning, and a buried portion that remains protected within the electrode structure. This segmentation allows the etch process to selectively remove only the protruding excess material while preserving the functional layer characteristics
2Ease of manufacture
If a conventional planar fabrication process is used, then the ease of manufacture is improved, but the manufacturing precision of the variable resistance layer pattern deteriorates
Solution Approach 1:
The variable resistance layer is extended into the vertical dimension by forming it to protrude above the electrode surface. This dimensional extension provides an additional control parameter for patterning, allowing precise definition of the layer boundaries through vertical height control rather than relying solely on complex lateral etching processes
3Ease of manufacture
If the variable resistance layer is not buried in the electrode, then the ease of manufacture is improved, but the reliability and data storage characteristics deteriorate
Solution Approach 1:
The variable resistance layer is nested within the electrode structure, with the electrode material surrounding and embedding the variable resistance material. This nested configuration provides physical protection and electrical isolation, enhancing the stability of data storage characteristics while maintaining a relatively simple single-step formation process
Data Source
AI summary
An electronic device including a semiconductor memory is provided. The semiconductor memory includes a first electrode, a second electrode crossing the first electrode, and a variable resistance pattern positioned in an intersection region of the first electrode and the second electrode and buried in the first electrode.