Buried Via Substrate Layout for High-Density Flexible Interconnects
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Solution Overview
Problem
Existing microelectronic device manufacturing processes face challenges in achieving high via density and geometry flexibility due to the need for multiple transfers between foundries and assemblers, leading to constraints in flatness and contamination, particularly with TSV-last vias.
Innovation Solution
A substrate with pre-formed buried vias, allowing for independent fabrication of vias that can be filled with conductive or semiconductive materials, facilitating integration into microelectronic devices without relying on other manufacturing stages, and enabling adaptable via geometries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If TSV-last vias are manufactured after FEOL and BEOL stages, then the number of transfers between foundry and assembler is reduced, but the via density and geometry flexibility are limited
Solution Approach 1:
The manufacturing process is segmented into independent stages: via formation is performed separately from device fabrication. The substrate is divided into a device region and a via region, allowing via patterning to be completed independently before assembly, thus enabling both reduced transfers and maintained geometry flexibility
Solution Approach 2:
Via patterning and formation are performed as preliminary actions before the final assembly stage. The vias are pre-formed in the substrate with desired geometries and positions, then the substrate is assembled with the device. This preliminary via formation enables geometry flexibility while reducing the number of transfers needed during later stages
2Ease of manufacture
If multiple transfers between foundry and assembler are performed, then via fabrication can be integrated with device manufacturing, but constraints in flatness and contamination increase
Solution Approach 1:
The process is segmented so that via formation occurs in separate regions of the substrate during independent fabrication stages. The device is fabricated in one region while vias are formed in another, then both are integrated in the final assembly. This segmentation allows each stage to be optimized independently, maintaining precision while enabling integration
Solution Approach 2:
The substrate acts as an intermediary carrier that holds both the device and via structures. The via region serves as a mediator element that can be fabricated independently and then integrated with the device region, reducing the need for repeated transfers between foundry and assembler while maintaining control over flatness and contamination
3Adaptability or versatility
If vias are formed with high density and flexible geometries, then substrate adaptability is enhanced, but the manufacturing process complexity increases
Solution Approach 1:
The substrate is segmented into device fabrication regions and via formation regions that can be processed independently. This allows high-density via patterns with flexible geometries to be created in dedicated via regions using specialized processes, while the device regions follow standard fabrication flows, thereby enhancing substrate adaptability without proportionally increasing overall manufacturing complexity
Solution Approach 2:
The substrate is designed with multi-functionality, serving both as the device platform and as the via carrier. The same substrate structure accommodates both device fabrication and high-density via formation, enabling substrate adaptability for various device configurations while using a universal manufacturing approach that reduces overall process complexity
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 3A~3B
AI summary
The invention relates to a substrate (3) comprising a semiconductor-based first layer (30), and a second layer (31) located above the first layer. The substrate (3) contains a plurality of buried vias (32) extending from the second layer (31) over a segment of the first layer (30), each via (32) being bounded by a sidewall (320), a bottom wall (321), and a top wall (322) that is opposite the bottom wall (321), and at least one set (32a) of the plurality of vias (32) forms a pattern (32b) that repeats in at least one direction of the plane of main extension of the first and second layers (30, 31). The substrate (3) thus forms a generic substrate allowing use of vias to fabricate a microelectronic device to be facilitated.