Buried Hollow Via Substrates for Planar High-Density TSVs
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Solution Overview
Problem
Existing methods for manufacturing through-silicon vias (TSVs) in microelectronic devices are limited by planarity and contamination issues during back-and-forth transfers between founder and assembler premises, and TSV geometries are constrained, particularly affecting high-density via applications like calculation.
Innovation Solution
A substrate with buried hollow vias is provided, allowing for independent via formation before FEOL and BEOL steps, using dielectric material walls for isolation and enabling high-temperature compatibility, with methods for etching and assembly to create a via matrix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV-middle vias are manufactured in the middle of the production line after FEOL but before BEOL, then via interconnection functionality is achieved, but substrate transfers between founder and assembler premises cause planarity and contamination issues
Solution Approach 1:
The substrate manufacturing process is segmented into independent stages: FEOL at founder premises, then substrate transfer to assembler premises for via formation and BEOL completion. This segmentation allows via formation to occur at the assembler location, eliminating the need for back-and-forth transfers and associated planarity/contamination issues.
Solution Approach 2:
Hollow vias are formed preliminarily at the assembler premises before BEOL metal layer deposition. This preliminary via formation with precise geometry control resolves the planarity and contamination issues that would otherwise occur during later processing stages at the founder premises.
2Device complexity
If TSV-last vias are manufactured at the end of the method after FEOL and BEOL steps, then substrate transfer complexity is reduced, but via density and geometry are limited
Solution Approach 1:
Hollow vias are formed preliminarily at the assembler premises before BEOL metal layer deposition. This preliminary via formation with precise geometry control resolves the planarity and contamination issues that would otherwise occur during later processing stages at the founder premises.
3Reliability
If metallised vias are used in current solutions, then electrical conductivity is achieved, but compatibility with high-temperature FEOL steps is problematic
Solution Approach 1:
Hollow vias are formed preliminarily at the assembler premises before BEOL metal layer deposition. This preliminary via formation with precise geometry control resolves the planarity and contamination issues that would otherwise occur during later processing stages at the founder premises.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates via manufacturing by allowing independent via formation, improving via density and geometry without limiting other steps, enhancing planarity and reducing contamination, suitable for high-density interconnects.
Implementation Method 1
an etching of a plurality of vias, such that the vias extend from the exposed surface over a portion of the first layer
Data Source
AI summary
A substrate is provided, including: a first layer based on a semiconductive material; a second layer surmounting the first layer; and a plurality of buried vias extending from the second layer over a portion of the first layer, each via of the plurality of buried vias being delimited by a side wall, a bottom wall, and an upper wall opposite the bottom wall, each via having at least one transverse dimension less than or equal to 30 μm. A method for manufacturing the substrate is also provided. A method for manufacturing a microelectronic device is also provided.