Dual-Channel Buried Waveguide With Self-Aligned Current Confinement

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Solution Overview

Problem

Existing methods for manufacturing buried heterostructure optoelectronic components, such as lasers and semiconductor optical amplifiers, face challenges including high costs due to the need for expensive ion implanters, risk of contamination, complex lithography alignment, and potential damage to semiconductor structures from ion implantation, as well as dependency on selective epitaxial regrowth which complicates the fabrication process.

Innovation Solution

A dual-channel buried waveguide apparatus with self-aligned electrical insulation is fabricated using a simplified method that defines narrow current injection areas in a single lithography step, eliminating the need for ion implantation and selective regrowth, by forming inverted T-shaped trenches on either side of the waveguide to prevent current leakage and using insulating materials to fill voids, thereby reducing fabrication complexity and improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation is used to define current injection areas, then current leakage is prevented, but fabrication cost increases and semiconductor structures may be damaged

Engineering Contradiction:
Improvecurrent leakage preventionVSAvoidfabrication cost and complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates the ion implantation step from the fabrication process. Instead of using ion implantation to define current injection areas, the invention uses a simplified approach where current injection areas are defined by the waveguide structure itself, removing the need for expensive ion implanters and complex alignment procedures while maintaining effective current leakage prevention

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive, complex ion implantation equipment and processes with simpler, more economical fabrication methods. The current injection areas are defined using standard lithography and etching processes that are already part of typical semiconductor manufacturing, eliminating the need for specialized ion implantation equipment and reducing overall fabrication costs

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If selective epitaxial regrowth is used to bury the waveguide, then good electrical injection is achieved, but fabrication process becomes complex

Engineering Contradiction:
Improveelectrical injection qualityVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the selective epitaxial regrowth step from the fabrication process. Instead of using selective regrowth to bury the waveguide and achieve good electrical injection, the invention uses a simplified approach where the waveguide is buried using standard deposition and etching processes, maintaining electrical injection quality while removing the complexity of selective regrowth

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the waveguide burial process with standard semiconductor fabrication steps. Instead of using a separate, complex selective epitaxial regrowth process, the burial is achieved through integrated deposition and etching steps that are already part of typical manufacturing flows, reducing overall process complexity

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If narrow current injection areas are defined in a single lithography step, then alignment precision requirements are reduced, but current leakage prevention becomes more challenging

Engineering Contradiction:
Improvelithography alignment simplicityVSAvoidcurrent leakage prevention
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by creating distinct regions with different properties. The current injection areas are defined with narrow widths in a single lithography step, while the surrounding areas are treated differently through selective etching and filling processes. This local differentiation ensures that current is confined to the narrow injection areas while preventing leakage in the surrounding regions, achieving both alignment simplicity and leakage prevention

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP4080698B1Dual-channel buried waveguide and method for fabricating the same
Publication Date: 2024.03.13 NOKIA SOLUTIONS & NETWORKS OY
  • EP4080698B1 patent drawingFigure 1A~1B
  • EP4080698B1 patent drawingFigure 2~3B
  • EP4080698B1 patent drawingFigure 4~5

AI summary

A general embodiment relates to an apparatus (1) comprising a first cladding semi-conductor layer stack (2) of a first conductivity type, an active semi-conductor layer stack (3) for producing optical gain and/or light emission, said active semi-conductor layer stack (3) being formed on said first cladding semi-conductor layer (2) and buried under a second cladding semi-conductor layer stack (4) of a second conductivity type, comprising at least one regrowth layer (41). An integrated dual-channel buried waveguide (W) is formed along the longitudinal axis of the apparatus (1) and comprises at least one central stripe portion (S) with a dual channel (C) of two channels (C1, C2) buried in a semi-conductor layer stack (5) and formed along both sides of the stripe (S) and extending through the first cladding semi-conductor layer stack (2), the active semi-conductor layer stack (3) and the second cladding semi-conductor layer stack (4). On respective edges of the channels (C1, C2) which are opposite the central strip portion (S), there are lateral zones (Ll, L2) within which there are vertical trenches (Tl, T2) perpendicular to the longitudinal axis of the apparatus and crossing through the thickness of the apparatus (1) up to the level of the active layer stack (3), said vertical trenches (Tl, T2) extending longitudinally through the entire thickness of said active layer stack (3) up to the edges of the channels (C1, C2) which are opposite the central strip portion (S), so as to form respectively two spaces (V1, V2) located in the lateral zones (Ll, L2) and having each the shape of an inverted T.