Buried-Well Image Sensor Pixel Architecture for High Sensitivity
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in achieving high sensitivity and low full-well capacity, which are essential for advanced image sensors like Quanta Image Sensors (QIS) and Digital Integration Sensors (DIS), as they require careful circuit design to ensure complete charge transfer and often necessitate overvoltages or bootstrapping, making it difficult to scale pixels for higher density and sensitivity.
Innovation Solution
The development of an image sensor pixel architecture with a buried-well vertically pinned photodiode and a floating diffusion region, where the charge accumulation/storage region has a full-well capacity less than 3000 charge carriers, and a transfer gate that selectively controls charge transfer between the accumulation/storage region and the floating diffusion, allowing for high conversion gain and compact pixel design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the full-well capacity is increased to improve dynamic range and signal-to-noise ratio, then the depth of the photodiode well and floating diffusion capacitance must be increased, but this exacerbates charge transfer problems and requires higher reset voltages or bootstrapping
Solution Approach 1:
The patent introduces a vertical stacking dimension by placing the photodiode beneath the transfer gate, moving from a planar to a three-dimensional architecture. This allows the photodiode depth to be increased for higher full-well capacity without increasing the lateral pixel area, and enables independent optimization of charge storage depth and transfer gate control
Solution Approach 2:
The patent segments the charge transfer process into controlled phases by dividing the transfer gate into multiple independently controllable gates (first transfer gate and second transfer gate). This segmentation allows precise control over charge transfer timing and prevents charge loss by managing the transfer process in discrete steps rather than a single passive transfer
2Area of moving object
If the pixel size is reduced to achieve higher density, then the full-well capacity decreases, but this compromises the signal-to-noise ratio and dynamic range
Solution Approach 1:
By stacking the photodiode vertically beneath the transfer gate, the patent increases the charge storage capacity in the vertical dimension while maintaining a compact lateral footprint. This allows small pixel areas to achieve sufficient full-well capacity for good signal-to-noise ratio
Solution Approach 2:
The patent nests the photodiode structure within the pixel area by positioning it beneath the transfer gate, effectively utilizing the vertical space under existing lateral components. This nesting allows the photodiode to occupy the same lateral footprint as the transfer gate while providing additional charge storage depth
3Manufacturing precision
If conventional pinned photodiode architecture is used with intra-pixel charge transfer, then the floating diffusion must be reset to high voltage to ensure complete charge transfer, but this increases power consumption and circuit complexity
Solution Approach 1:
The patent implements dynamic control of the transfer gate voltage, switching between different voltage states (first voltage and second voltage) to control charge transfer timing. This dynamic approach allows complete charge transfer without requiring the floating diffusion to be reset to excessively high voltages, as the transfer is controlled by the gate voltage transitions rather than passive potential differences
Solution Approach 2:
The patent applies preliminary control voltages to the transfer gate before charge transfer is needed, preparing the transfer path in advance. By pre-biasing the transfer gate and controlling the timing of voltage transitions, the system ensures complete charge transfer without requiring high reset voltages on the floating diffusion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of compact, high-sensitivity image sensor pixels suitable for QIS, qDIS, and DIS applications, while also being applicable to conventional CMOS image sensors, by eliminating the need for high full-well capacity and reducing charge lag and noise, thus enhancing sensitivity and scalability.
Implementation Method 1
the photodetecting element is typically a pinned photodiode (PPD), and the signal charge integrated in the PPD
Data Source
AI summary
Image sensor pixels having low full-well capacity and high sensitivity for applications such as DIS, qDIS, single/multi bit QIS. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate. Image sensor may also comprise an array of pixels, wherein each pixel comprises: a vertical bipolar structure including an emitter, base, collector configured for storing photocarriers in the base; and a reset transistor coupled to the base, configured to be completely reset of all free carriers using the reset transistor. The emitter may be configured as a pinning layer to facilitate full depletion of the base. Such image sensor pixels may have a full well capacity less than that giving good signal-to-noise ratio (SNR).