Buried Wiring ESD Protection Layout for Semiconductor I/O

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Solution Overview

Problem

Configurations of semiconductor devices incorporating buried power supply wirings for ESD protection circuits have not been thoroughly studied, limiting the implementation of effective ESD protection in semiconductor devices.

Innovation Solution

A semiconductor device design that includes a substrate with a circuit region featuring a power supply wiring, a ground wiring, and a signal line, with a diode connected between the signal line and one of the power supply or ground wirings, where the diode has impurity regions of different conductive types, allowing for the implementation of an ESD protection circuit using buried wirings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If power supply wirings are provided above substrates, then ease of manufacture is improved, but device area increases

Engineering Contradiction:
Improveease of manufactureVSAvoiddevice area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent transitions power supply wirings from a planar configuration (above substrate) to a three-dimensional buried structure (within substrate), utilizing the vertical dimension to reduce the horizontal area occupied by power supply networks while maintaining manufacturing feasibility through established semiconductor fabrication processes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If power supply wirings are buried in substrates, then device area is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvedevice areaVSAvoidmanufacturing complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent combines the power supply wiring formation process with existing substrate processing steps, integrating buried wiring creation into the standard fabrication sequence rather than adding separate complex manufacturing stages, thereby reducing overall manufacturing complexity while achieving area reduction

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If ESD protection circuits are implemented with traditional configurations, then reliability is improved, but device area increases

Engineering Contradiction:
ImprovereliabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent embeds ESD protection circuit elements within the buried power supply wiring structure itself, nesting the protection functionality inside the existing power distribution framework, which reduces the overall area required for ESD protection while maintaining the reliability benefits of dedicated protection circuits

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the implementation of an ESD protection circuit with buried wirings, enhancing the miniaturization and current uniformity of semiconductor devices while reducing parasitic capacitance and improving layout flexibility.

Implementation Method 1

The I/O cell region may be provided with an ESD (Electro-Static Discharge) protection circuit to suppress breakdown of the internal circuit region due to static electricity

Methodology Applied
Scientific EffectElectrostatic Discharge: Electrostatic Discharge

Data Source

PatentUS12199089B2Semiconductor device
Publication Date: 2025.01.14 SOCIONEXT INC
  • US12199089B2 patent drawing
  • US12199089B2 patent drawing
  • US12199089B2 patent drawing

AI summary

A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.