Buried Wiring in Vertical Transistor Substrates
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Solution Overview
Problem
As semiconductor devices become increasingly integrated, multi-layered wiring structures face challenges such as resolution limits in photolithography processes and parasitic capacitances, making it difficult to maintain electrical characteristics and ensure process margins, particularly in memory cell regions.
Innovation Solution
A substrate structure is developed with a buried wiring interposed between two substrates, where the buried wiring is in direct contact with one substrate and serves as a source or drain electrode of a vertical transistor, and a method of fabrication involving the formation of insulating and barrier layers, sacrificial layers, and attachment techniques is employed to create this structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-layered wiring structures are used to increase integration, then wiring density is improved, but parasitic capacitances increase and electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from planar multi-layered wiring to three-dimensional vertical transistors with buried wiring. The active channel extends vertically into the substrate, allowing source and drain regions to be positioned at different depths. This spatial reconfiguration reduces parasitic capacitance between adjacent wirings by separating them in the vertical dimension while maintaining high integration density.
Solution Approach 2:
The patent introduces a buried wiring layer positioned between the first substrate and the vertical transistor structure. This intermediary wiring layer serves as a dedicated interconnection that reduces parasitic capacitance by providing a direct electrical path without requiring proximity to other active devices, thereby improving electrical characteristics while maintaining high wiring density.
2Quantity of substance
If design rules are decreased to increase integration, then device density is improved, but photolithography resolution limits are exceeded and process margins are reduced
Solution Approach 1:
The patent employs vertical transistors where the channel extends in the depth direction rather than laterally. This allows device density to increase by utilizing the vertical dimension, while the photolithography process only needs to define the lateral footprint and depth of the structures. Consequently, design rules can be relaxed in the lateral direction, maintaining adequate process margins while achieving high integration.
Solution Approach 2:
The patent segments the transistor structure into distinct lateral and vertical components. The gate electrode, source/drain regions, and buried wiring are positioned at different vertical levels, allowing each component to be formed with appropriate process parameters. This segmentation enables the use of standard photolithography for lateral patterning while achieving high density through vertical stacking, thus preserving process margins.
3Quantity of substance
If wiring structures are increasingly integrated, then wiring density is improved, but electrical characteristics are adversely impacted
Solution Approach 1:
The patent achieves high wiring density by stacking wiring layers vertically and positioning source/drain regions at different depths. This three-dimensional arrangement reduces the lateral proximity between conductive elements, thereby minimizing parasitic capacitance and crosstalk. The result is improved electrical characteristics including higher speed and lower power consumption while maintaining high integration density.
Solution Approach 2:
The buried wiring layer acts as an intermediary that provides dedicated interconnection paths separated from other active devices. This isolation reduces parasitic capacitance and improves signal integrity, thereby enhancing electrical characteristics such as switching speed and power efficiency while maintaining high wiring density through vertical stacking.
Data Source
AI summary
A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure. The vertical transistor includes a gate electrode and a semiconductor pillar, and the buried wiring is one of source electrode or a drain electrode of the vertical transistor.