Buried Word Line Etch-Back for Matched Surface Heights

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Solution Overview

Problem

The etch-back process for forming buried word lines in semiconductor structures often results in variations in the heights of the materials due to etching selectivity issues, leading to inconsistent buried word line structures.

Innovation Solution

The method involves a multi-stage etching process with different plasma etching selectivities and power adjustments in a single etching chamber, ensuring that the top surfaces of the etched dielectric and gate electrode materials are maintained at a substantially identical level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single etch-back process is used to form buried word lines, then the process is simple and fast, but the etching selectivity causes variations in heights of the materials for forming the buried word lines

Engineering Contradiction:
Improveetch-back process efficiencyVSAvoidheight consistency of buried word line materials
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The single etch-back process is divided into multiple sequential etch-back processes, each with different etching selectivities. The first etch-back process uses a first plasma with a first etching selectivity to recess the gate electrode material, while the second etch-back process uses a second plasma with a second etching selectivity to recess the dielectric material. This segmentation allows independent control of etching rates for different materials, resolving the height variation problem while maintaining overall process efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic adjustment of plasma parameters by switching between different plasma conditions (first plasma and second plasma) during the etch-back process. Each plasma type provides different etching selectivities, enabling adaptive control of the etching rate for specific materials. This dynamic approach allows precise control over the final heights of gate electrode material and dielectric material, eliminating height variations caused by static single-plasma processes.

Inventive Principle:
Principle #15Dynamics

2Manufacturing precision

If different plasma etching selectivities are used in multiple stages, then the height consistency of buried word line materials is improved, but the etching process complexity increases

Engineering Contradiction:
Improveheight consistency of buried word line materialsVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Multiple etch-back processes with different plasma selectivities are merged into a single continuous etching chamber operation. The first etch-back process and second etch-back process are performed sequentially without breaking the vacuum, eliminating the need for separate processing equipment and reducing overall process complexity. This merging approach maintains manufacturing precision while minimizing device complexity by integrating multiple functions into one system.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single etching chamber is designed to perform multiple functions by supporting different plasma types and etching selectivities within the same device. The etching chamber can switch between first plasma conditions and second plasma conditions, making it a universal tool that handles both the first etch-back process and second etch-back process. This multi-functionality reduces the need for multiple specialized devices, simplifying the overall manufacturing system while maintaining high precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If the top surfaces of dielectric material and gate electrode material are etched to different levels, then the etching process is simpler, but the buried word line structure consistency deteriorates

Engineering Contradiction:
Improveetching process simplicityVSAvoidburied word line structure consistency
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The etching process incorporates feedback control by monitoring the etching depth and adjusting plasma parameters accordingly. During the first etch-back process, the etching of gate electrode material is monitored and controlled to achieve the target depth. Then during the second etch-back process, the etching of dielectric material is monitored and adjusted to ensure its top surface aligns with the etched gate electrode material surface. This feedback mechanism ensures structure consistency while maintaining manufacturing simplicity.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for precise control of the etch-back process, resulting in buried word lines with consistent dimensions and improved integration density in semiconductor structures.

Implementation Method 1

performing an etching process to partially remove the dielectric material and gate electrode material exposed by the hard mask

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 2

the etching selectivity generally causes variations in heights of the materials for forming the buried word lines

Methodology Applied
Scientific EffectEtching selectivity:

Data Source

PatentUS12267993B2Semiconductor structure having buried word lines
Publication Date: 2025.04.01 NAN YA TECH
  • US12267993B2 patent drawing
  • US12267993B2 patent drawing
  • US12267993B2 patent drawing

AI summary

The present disclosure provides a method of forming a semiconductor structure. The method includes providing a substrate including an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.