Buried Word Line Interconnect Structure for Semiconductor Integration
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Solution Overview
Problem
Conventional techniques for forming buried word lines in semiconductor devices, such as using bypass interconnects and contact plugs, result in complex structures that hinder high integration and degrade electrical characteristics and reliability due to signal transmission path lengthening and difficulty in forming contact plugs.
Innovation Solution
A semiconductor device with a buried word line and a unitary word line interconnect that contacts the buried word line and extends vertically to connect with a gate line, eliminating the need for contact plugs and simplifying the structure by using a common metal layer for the word line and interconnect, which are formed at the same level as the buried word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bypass interconnect and contact plug are used to electrically connect the buried word line with the gate line, then the electrical connection is achieved, but the structure becomes complex and the signal transmission path is lengthened
Solution Approach 1:
The patent merges the bypass interconnect and contact plug into a single integrated structure. The word line interconnect is formed as a continuous conductive element that extends from the buried word line region through the interlayer insulating layers to contact the gate line, eliminating the need for separate contact plugs and multiple interlayer insulating layers. This unified structure reduces complexity while maintaining reliable electrical connection.
Solution Approach 2:
The patent extracts and eliminates the contact plug component from the conventional interconnect structure. By forming the word line interconnect as a continuous conductive layer that directly bridges the buried word line and gate line without requiring penetration through multiple insulating layers, the contact plug is removed entirely, simplifying the structure and shortening the signal path.
2Reliability
If a bypass interconnect and contact plug are used to electrically connect the buried word line with the gate line, then the electrical connection is achieved, but the signal transmission path is lengthened
Solution Approach 1:
The patent merges the bypass interconnect and contact plug into a single integrated structure. The word line interconnect is formed as a continuous conductive element that extends from the buried word line region through the interlayer insulating layers to contact the gate line, eliminating the need for separate contact plugs and multiple interlayer insulating layers. This unified structure reduces complexity while maintaining reliable electrical connection.
3Reliability
If contact plugs are used to penetrate the interlayer insulating layers, then the electrical connection is achieved, but the manufacturing difficulty increases
Solution Approach 1:
The patent extracts and eliminates the contact plug component from the conventional interconnect structure. By forming the word line interconnect as a continuous conductive layer that directly bridges the buried word line and gate line without requiring penetration through multiple insulating layers, the contact plug is removed entirely, simplifying the structure and shortening the signal path.
Solution Approach 2:
The patent segments the interconnect formation process into distinct regions: a first portion in the cell region at the same level as the buried word line, and a second portion in the peripheral circuit region that contacts the gate line. This segmentation allows each portion to be optimized for its specific function and formed using appropriate manufacturing techniques without requiring complex contact plug formation.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.