Buried Word Line Selectors for High-Density 3D NAND Memory
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Solution Overview
Problem
Existing 3D NAND non-volatile memory devices face challenges in achieving high-density memory arrays due to the significant area consumption of select gate transistors, which limits their ability to achieve high-density designs.
Innovation Solution
The implementation of buried word line selectors, where select gate transistors are disposed in the substrate below the NAND strings, allowing for the use of buried word lines as selector devices to form high-density 3D NAND non-volatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If select gate transistors are implemented in conventional positions, then memory device functionality is achieved, but area consumption increases significantly
Solution Approach 1:
The patent moves select gate transistors from the planar surface to the vertical dimension by embedding them in substrate trenches below the memory hole level. This dimensional transition allows select gate transistors to occupy vertical space rather than horizontal area, enabling high-density memory arrays without sacrificing device functionality.
Solution Approach 2:
The select gate transistors are nested within substrate trenches that are positioned below the memory hole level. This nesting arrangement allows the select gate transistors to be embedded within the substrate structure itself, effectively utilizing the vertical space beneath the memory cells to reduce overall area consumption.
2Quantity of substance
If memory array density is increased, then storage capacity improves, but select gate transistor area consumption becomes more significant
Solution Approach 1:
By transitioning select gate transistors from planar to vertical positioning in substrate trenches, the patent enables memory array density to increase without proportionally increasing select gate transistor area consumption. The vertical embedding allows multiple memory layers to share the same select gate transistor footprint.
Solution Approach 2:
The buried select gate transistors in substrate trenches serve multiple memory layers simultaneously, allowing a single select gate transistor to control access to multiple stacked memory cells. This multi-functionality increases memory array density while keeping the select gate transistor area consumption constant.
Data Source
AI summary
A method is provided that includes forming a three-dimensional NAND stacked non-volatile memory array on a substrate, and forming a DRAM memory array on the substrate. The three-dimensional NAND stacked non-volatile memory array and the DRAM memory array are formed using a single integrated circuit fabrication process.