Buried Word Line Structure for Semiconductor Reliability
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Solution Overview
Problem
Conventional semiconductor devices with metal gate electrodes, such as titanium nitride, experience degradation of oxide layers due to chlorine ion diffusion, leading to increased leakage current and reduced reliability, particularly at operation voltages below −3V.
Innovation Solution
A semiconductor device with a buried word line structure is developed, where the gate electrode and word line are completely buried within the substrate, using materials like polysilicon for the gate electrode and titanium nitride for the word line, formed using chemical vapor deposition or atomic layer deposition methods, to reduce the device height and prevent oxide layer degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a TiN layer is formed by CVD method using TiCl4 and NH3 to secure step coverage above 10:1, then the gate electrode structure is improved, but chlorine ions diffuse into oxide layers and silicon channels forming traps, causing degradation characteristics
Solution Approach 1:
A barrier layer is introduced as an intermediary between the TiN gate electrode and the oxide layer. This barrier layer prevents chlorine ions from the TiN layer from diffusing into the oxide layer and silicon channels, thereby eliminating trap formation while maintaining the beneficial step coverage properties of the TiN layer
Solution Approach 2:
The harmful chlorine ions are extracted or blocked from reaching the oxide layer by the barrier layer. The barrier layer specifically targets and prevents the diffusion of chlorine contaminants, separating the source of contamination (TiN layer) from the vulnerable components (oxide layer and silicon channels)
2Device complexity
If the metal gate electrode protrudes beyond the substrate surface to serve as both gate electrode and word line, then the device structure is simplified, but the semiconductor device height increases, making it unsuitable for thinner devices
Solution Approach 1:
The gate electrode structure is transitioned from a protruding three-dimensional configuration to a planar, coplanar configuration where the gate electrode and word line lie in the same plane as the substrate surface. This dimensional reorganization eliminates vertical protrusion while maintaining electrical functionality through lateral extension
Solution Approach 2:
The gate electrode and word line functions are merged into a single coplanar structure. By forming both elements in the same plane without protrusion, the design simplifies the overall device architecture while reducing height, allowing both functions to be achieved through lateral rather than vertical separation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buried word line structure reduces the height of the semiconductor device, minimizes oxide layer degradation, and improves reliability by maintaining low leakage current and thermal stability, enhancing the overall performance and longevity of the device.
Implementation Method 1
a gate insulating layer on the surface of the trench
Implementation Method 2
forming a polysilicon layer on the surface of the gate insulating layer
Implementation Method 3
formed using chemical vapor deposition or atomic layer deposition methods
Data Source
AI summary
Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.