Buried Word Line Vertical Gate Device for Low Resistance
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Solution Overview
Problem
As semiconductor devices approach the physical limitations of scaling in the planar direction, maintaining low word line resistance becomes challenging, especially when reducing gate sizes for vertical transistors, which can lead to increased power consumption and operational issues due to higher voltages needed to offset resistance increases.
Innovation Solution
The implementation of buried word lines and bit lines, separated from the gates by insulation, allows for sufficient thickness to maintain manageable resistance, with interposers coupling these lines to the gates, enabling efficient signal application without the need for thinner word lines, thus reducing the impact of pillar density on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If word lines are integrated with gates in vertical transistors to reduce cell size, then device density is improved, but word line resistance increases
Solution Approach 1:
The patent segments the word line function from the gate structure by providing buried word lines separate from the vertical gates. This allows the word lines to be optimized for low resistance independently from the gate dimensions, resolving the contradiction between high density and low resistance by separating these two functions spatially.
Solution Approach 2:
The patent moves the word lines to a different dimensional plane by burying them below the pillar level, while gates remain on the pillar surfaces. This vertical separation in the third dimension allows both compact cell design and sufficient word line thickness for low resistance.
2Quantity of substance
If pillars are brought closer together to increase density, then device capacity is improved, but word line resistance increases due to thinner lines
Solution Approach 1:
By segmenting the word line into a separate buried structure independent from the gate, the word line thickness is no longer constrained by the pillar spacing. This allows pillars to be densely packed while maintaining sufficient word line thickness for low resistance.
Solution Approach 2:
The patent introduces interposers as intermediary structures that connect the buried word lines to the vertical gates. This intermediary connection allows the word lines to remain thick and low-resistance while still providing electrical connection to the densely packed pillars.
3Area of stationary object
If word line thickness is reduced to accommodate smaller cell sizes, then cell density is improved, but power consumption increases due to higher resistance
Solution Approach 1:
The patent segments the word line into a separate buried structure that can maintain optimal thickness independent of cell size reduction. This allows small cell dimensions while keeping word line thickness sufficient for low resistance and low power consumption.
Solution Approach 2:
The patent changes the spatial parameter of the word line by burying it below the pillar level, which decouples the word line thickness parameter from the cell size parameter. This allows independent optimization of both cell density and resistance.
Data Source
AI summary
A semiconductor device includes a substrate having a primary side. A first pillar extends vertically with respect to the primary side of the substrate, the first pillar defining first and second conductive regions and a channel region that is provided between the first and second conductive regions. A first gate is provided over the channel region of the first pillar. A buried word line extends along a first direction below the first pillar, the buried word line configured to provide a first control signal to the first gate. A first interposer is coupled with the buried word line and the first gate to enable the first control signal to be applied to the first gate via the buried word line.