Buried Word Line Work Function Tuning for DRAM Row Hammer Prevention

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Solution Overview

Problem

The row hammering issue in DRAM cells causes intermittent failures due to charge migration and data corruption, which existing solutions attempt to address by limiting access or reducing refresh time, but these methods impact performance and have physical limitations.

Innovation Solution

A semiconductor structure is developed with an n-type work function metal layer, including titanium and titanium nitride, to tune the work function of the buried word line, preventing leakage to adjacent rows, comprising a substrate, trench, gate dielectric, and buried word line with a gradually increasing titanium nitride to titanium ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of accesses per row per refresh cycle is limited to address row hammer failure, then data corruption is reduced, but system performance deteriorates

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

An intermediate layer (first work function metal layer) is introduced between the bit line contact and the buried channel array transistor to prevent direct charge migration. This intermediary structure blocks the harmful electron flow path while allowing normal memory operations, thus protecting data integrity without limiting access frequency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the harmful effect of repeated row access (which causes charge migration) into a beneficial protective mechanism. By designing the work function metal layer with specific properties, the structure that would normally be vulnerable to row hammering is transformed into an active defense mechanism that prevents charge migration while maintaining normal access operations.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If the bottom critical dimension in the buried channel array transistor is decreased to address row hammer failure, then charge migration is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvecharge migration preventionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of changing the critical dimensions of the transistor, the patent changes the material parameters of the work function metal layer. By adjusting the work function and material composition (using titanium nitride and titanium in specific ratios), the patent achieves charge migration prevention through electrical property modification rather than geometric dimension changes, avoiding increased manufacturing complexity.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the time between refreshes is decreased to prevent row hammering, then data corruption is reduced, but refresh overhead increases

Engineering Contradiction:
Improvedata integrityVSAvoidrefresh overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The protective work function metal layer structure is built in advance during manufacturing, providing inherent protection against row hammering before any access operations occur. This preliminary structural defense eliminates the need for frequent refresh operations or access limiting, as the charge migration path is blocked by design rather than by operational constraints.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively prevents row hammering without significantly altering the DRAM or DIMM design, maintaining performance while reducing data corruption and failure rates.

Implementation Method 1

an n-type work function metal layer to tune the work function of the buried word line, thereby preventing the row hammering issue resulted from the word line leakage to a non-accessed physically adjacent row

Methodology Applied
Scientific EffectWork function:

Data Source

PatentUS11239243B2Semiconductor structure for preventing row hammering issue in DRAM cell and method for manufacturing the same
Publication Date: 2022.02.01 UNITED MICROELECTRONICS CORP
  • US11239243B2 patent drawing
  • US11239243B2 patent drawing
  • US11239243B2 patent drawing

AI summary

A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.