Buried Wordline Memory Structure With Variable Channel Widths
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Solution Overview
Problem
Current semiconductor memory technologies, such as DRAM and MRAM, face challenges in implementing the buried wordline structure due to differences in drive current requirements, limiting storage density and cell size reduction in MRAMs.
Innovation Solution
A semiconductor structure is proposed with a substrate featuring first and second transistors with channels of different widths, where the second channel is wider than the first, allowing for compatible fabrication techniques and increased drive current, enhancing integration density and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a buried wordline structure is used to enhance storage density, then storage density is improved, but drive current requirements cannot be met for MRAM
Solution Approach 1:
The patent applies local quality by creating different channel widths for different transistor types within the same memory structure. First transistors (for DRAM) have narrower channels optimized for low leakage current, while second transistors (for MRAM) have wider channels optimized for high drive current. This allows each transistor type to have locally optimized properties suitable for its specific function while sharing the same buried wordline structure.
2Reliability
If different drive currents are required for DRAM and MRAM, then device performance is optimized, but implementation of unified buried wordline structure becomes impossible
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through variable channel widths. The first transistors have first channel widths optimized for DRAM operation with small drive currents, while the second transistors have second channel widths optimized for MRAM operation with large drive currents. This allows a unified buried wordline structure to serve both transistor types with their different current requirements.
Solution Approach 2:
The patent applies universality by designing a single buried wordline structure that serves dual functions: controlling both DRAM transistors and MRAM transistors. The buried wordline acts as a common control element for both transistor types, enabling the structure to be universal while still accommodating their different electrical requirements through the variable channel width design.
3Power
If channel width is increased to provide higher drive current, then drive current is improved, but leakage current increases
Solution Approach 1:
The patent applies local quality by assigning different channel widths to different transistor types based on their specific needs. First transistors have narrower channels that minimize leakage current for DRAM applications, while second transistors have wider channels that maximize drive current for MRAM applications. Each transistor type experiences locally optimized channel dimensions matched to its functional requirements.
Solution Approach 2:
The patent uses segmentation by dividing the memory structure into distinct regions with different transistor types and channel widths. The first transistors are segregated with narrow channels for low leakage, while the second transistors are segregated with wide channels for high drive current. This segmentation allows each segment to have optimized properties without adversely affecting the other segment.
Data Source
AI summary
The present application relates to a semiconductor structure and its forming method. The semiconductor structure comprises a substrate; a first transistor that includes a first channel disposed within the substrate, and a first end disposed at surface of the substrate, the first end being adapted to connect with a first-type storage cell; a second transistor that includes a second channel disposed within the substrate, and a second end disposed at surface of the substrate, the second end being adapted to connect with a second-type storage cell, the second channel having a length greater than length of the first channel. The present application enables fabrication techniques of the first transistor and the second transistor compatible. Moreover, the present application is conducive to enhancing integration density of the storage cells of the first transistor and/or the second transistor in the memory lays foundation for enlarging the fields of application of the memory.