Semiconductor Burn-In Test Circuit for Reduced Time
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Solution Overview
Problem
The increasing complexity of semiconductor device design and manufacturing leads to lengthy and costly test processes, particularly during the burn-in (TDBI) process, which requires a significant amount of time and resources.
Innovation Solution
A test method and semiconductor system that allow setting parameters for testing during one clock cycle using a command generation circuit, test control circuit, and test circuit, enabling faster and more efficient testing by generating internal commands and entering test modes, thereby reducing test time and equipment operation speed requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional test process is used for semiconductor devices with increased degree of integration, then measurement precision and reliability are improved, but test time becomes excessively long and costs increase
Solution Approach 1:
The patent applies preliminary action by performing built-in self-test (BIST) operations during the burn-in process before final packaging and testing. The test circuit executes write operations and pattern iterations during the burn-in period, utilizing the already-applied stress conditions to conduct preliminary testing that would otherwise require separate dedicated test time later in the manufacturing process.
Solution Approach 2:
The patent merges the burn-in process with the test process by integrating test operations into the burn-in procedure. The test control circuit combines stress application (burn-in) with test pattern generation and evaluation, allowing both processes to occur simultaneously during the same time period rather than sequentially, thereby reducing total manufacturing time.
2Loss of time
If a built-in self-test (BIST) circuit is used to test semiconductor devices before packaging, then test time is reduced, but device complexity increases
Solution Approach 1:
The test circuit is designed with multi-functionality to perform various test operations including write pattern generation, stress application control, and result evaluation. The same circuit infrastructure is used for both burn-in stress testing and functional testing, eliminating the need for separate dedicated test hardware and reducing overall device complexity despite the comprehensive testing capabilities.
3Reliability
If a lengthy test process is used to ensure device reliability, then product quality is improved, but productivity decreases
Solution Approach 1:
The patent ensures continuity of useful action by maintaining test operations throughout the entire burn-in period without interruption. The test control circuit continuously generates test patterns and monitors device performance during the burn-in stress period, maximizing the utilization of the burn-in time for dual purposes of stress testing and functional verification, thereby improving productivity without compromising reliability.
Data Source
AI summary
A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.